DESI - Trabajos de fin de Especialidad en Diseño de Sistemas en Chiphttps://hdl.handle.net/11117/34272024-03-28T17:18:52Z2024-03-28T17:18:52ZRegistro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicasGarza-Pérez, Raymundohttps://hdl.handle.net/11117/76912022-01-11T03:00:42Z2021-07-01T00:00:00ZRegistro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas
Garza-Pérez, Raymundo
This document presents the design of a successive approximation register (SAR) and a digital to analog converter (DAC). The two circuits are designed, synthesized, and implemented in layout using TSMC 180nm technology. The DAC has a Charge-Scaling Capacitors architecture and uses a switching scheme different to the conventional one, which improves the power consumption of the circuit. These modules are used in a low power 10-bit ADC and are designed for Biomedical applications. The SAR design is synthesized using a clock with a frequency of 250 MHz, the total power consumption of the SAR is 22045.030 uW. A testbench is designed to verify the functionality of the SAR by testing several cases of interest. The base capacitance of the DAC is 1 pF. The functionality of the DAC is tested using a mixed signal simulator and a testbench with the required circuit. This also includes the Verilog model of the SAR block. The testbench is able to apply single conversions test case and a ramp-test case, in which all the possible inputs to the DAC are tested sequentially.
2021-07-01T00:00:00ZVoltaje de referencia BandGap y módulo de comunicación serial para SAR ADC 10 bits de baja potencia para aplicaciones biomédicasGonzález-Ornelas, Luis A.https://hdl.handle.net/11117/76192021-10-30T03:00:42Z2021-10-01T00:00:00ZVoltaje de referencia BandGap y módulo de comunicación serial para SAR ADC 10 bits de baja potencia para aplicaciones biomédicas
González-Ornelas, Luis A.
The document presents two designs a BandGap Reference Voltage, and a Communication Serial Module for a 10 bits SAR ADC for low-power applications. Designs were implemented using TSMC 0.18 µm CMOS technology with 1.8 V supply voltage. The BandGap Reference Voltage was designed to provide a reference voltage of 900 mV ±500 µV. The bandgap was tested at simulation level under different temperature conditions to ensure constant output in a temperature range from –40 °C to 85 °C. The Communication Serial Module is designed using the hardware description language Verilog. This module receives the 10 bits parallel output of the SAR ADC and retransmits the conversion result into a serial format using the SPI format. The Communication Serial Module was tested under a simulator, where multiple test cases were applied to stimulate in different ways the module. Both circuits were designed to accomplish the SAR ADC requirements in which BandGap supplies the reference voltage to the capacitor array in the SAR ADC and the Serial Module sends the data values after the conversion is finalized.
2021-10-01T00:00:00ZDynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical ApplicationsCastañeda-Villalpando, Karinahttps://hdl.handle.net/11117/75562021-11-04T17:36:55Z2021-09-01T00:00:00ZDynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical Applications
Castañeda-Villalpando, Karina
This document presents the design of a Dynamic Comparator, a SR Latch and a Sample and Hold circuit for a 10 bits SAR ADC. Designs are performed using TSMC 0.18 um CMOS technology with 1.8 V supply voltage. The Dynamic comparator with Strong Arm topology is chosen to fulfill the requirements of SAR ADC. Its performance is tested at simulation level with a clock frequency of 10 KHz to 310 MHz, using typical parameter of process, nominal supply voltage and room temperature. Although, results are presented only at clock frequency of 100 KHz. This analysis showed that comparator has an input offset of 17.8 mV and power consumption of 36.27 nW. Power consumption is in the power budget of SAR ADC however, the input offset voltage has limited the resolution of SAR ADC. The SR latch is designed at transistor level using NAND gates. The circuit has additional digital logic and an external reset pin in order to avoid the prohibited condition. After implementing this modification, it shows a correct functionality at a clock frequency of 100 KHz. The sample and hold circuit is designed with a bootstrap switch for a load capacitance of 300 pF which is the total capacitance of the circuit when it is integrated to the SAR ADC.
2021-09-01T00:00:00ZImplementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS TechnologyMartínez-Flores, Ivánhttps://hdl.handle.net/11117/63922021-09-06T16:00:27Z2020-08-01T00:00:00ZImplementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology
Martínez-Flores, Iván
This document presents the design of an arbiter circuit for a time-based SAR-ADC. The arbiter is a TSPC D flip flop. It was designed in TSMC 0.18 µm CMOS technology with 1.8 V supply voltage. It was tested at a clock frequency of 200 KHz, but it can operate even at 100 MHz. Simulation results using the typical process parameters shown a setup time of 5.02 ps and Hold time of 51.72 ps, the TSPC D flip flop power consumption is 62.61 µW@200 KHz, and the layout area is 368.284 µm2.
The simulation is performed across all PVT corners that vary from a temperature of -40 °C up to 125 °C, with a supply voltage variation from 1.62 V up to 1.98 V and the TSPC D flip flop functionality is correct.
2020-08-01T00:00:00Z