Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology

Aguilera-Galicia, Cuauhtémoc R.Figueroa-Vázquez, Cristian F.2020-11-042020-11-042020-08Figueroa-Vázquez, C. F. (2020). Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.https://hdl.handle.net/11117/6384This document presents a 0.18 um CMOS process highly-linear Voltage-to-Time Converter (VTC) design that can operate at a low voltage of 1.8 V across PVT corners and with the power consumption of less than 13 uW and linearity error less than 1%. The VTC was designed to work at a minimum of 1.68 V and accepts a maximum clock frequency of 900 MHz; to reduce non-linear behavior a symmetric load and current starved inverter configuration was proposed. This circuit was designed using TSMC 0.18 um CMOS process technology.engVoltage-to-Time ConverterAnalog to Digital ConverterSuccessive Approximation RegisterDigital to Analog ConverterImplementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technologyinfo:eu-repo/semantics/academicSpecialization