Rangel-Patiño, Francisco E.Viveros-Wacher, AndrésRayas-Sánchez, José E.Duron-Rosales, IsmaelVega-Ochoa, Édgar A.Hakim, NagibLópez-Miralrio, Enrique2020-06-122020-06-122020-06F.E. Rangel-Patiño, A. Viveros-Wacher, J.E. Rayas-Sánchez, I. Durón-Rosales, E.A. Vega-Ochoa, N. Hakim, and E. López-Miralrio, A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation, IEEE Trans. Emerging Topics Computing,8( 2): 453-463, Apr.-Jun. 2020. DOI: 10.1109/TETC.2017.27579372376-4562https://hdl.handle.net/11117/6236There is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.engBit-error-rateDoEEqualizationEye-diagramHigh-speed serial I/OInterconnectsJitterKrigingOptimizationPost-Si validationReceiverSerDesTransmitterinfo:eu-repo/semantics/article