Rangel-Patiño, Francisco E.Viveros-Wacher, AndresRajyaguru, ChintanVega-Ochoa, Edgar A.Rodriguez-Saenz, Sofia D.Silva-Cortes, Johana L.Shival, HemanthRayas-Sánchez, José E.2023-08-142023-08-142023-06-30F. E. Rangel-Patiño, A. Viveros-Wacher, C. Rajyaguru, E. A. Vega-Ochoa, S. D. Rodriguez-Saenz, J. L. Silva-Cortes, H. Shival, and J. E. Rayas-Sánchez. “PCIe Gen5 physical layer equalization tuning by using K-means clustering and Gaussian process regression modeling in industrial post-silicon validation,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. (NEMO-2023), Winnipeg, MB, Canada, Jun. 2023, pp. 162-165.979-8-3503-4741-82575-4742https://hdl.handle.net/11117/9644Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry. The continuously increasing bandwidth demand from new applications has led to the development of the PCIe Gen5, reaching data rates of 32 GT/s. To mitigate undesired channel effects due to such high-speed, the PCIe specification defines an equalization process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding an optimal subset of Tx and Rx coefficients by measuring the eye diagrams across different channels. However, these experiments are very time consuming since they require massive lab measurements. In this paper, we use a K-means approach to cluster all available post-silicon data from different channels and feed those clusters to a Gaussian process regression (GPR)-based metamodel for each channel. We then perform a surrogate-based optimization to obtain the optimal tuning settings for the specific channels. Our methodology is validated by measurements of the functional eye diagram of an industrial computer platform.engClusteringEqualizationEqualization MapsEye-diagramFIRGPRHSIOHigh-speed LinksMetamodelsOptimizationPCIePost-silicon ValidationReceiverSignal IntegrityTransmitterTuninginfo:eu-repo/semantics/article