DESI - Trabajos de fin de Maestría en Diseño Electrónico
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Ítem Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators(ITESO, 2017-02) Trejo-Arellano, Juan M.; Longoria-Gándara, Omar H.; Vázquez-Castillo, JavierÍtem Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques(ITESO, 2021-02) Mercado-Casillas, Benjamín; Rayas-Sánchez, José E.Ítem Antenna Design Optimization Through Input Space Mapping(ITESO, 2020-05) Michel-Camacho, Eduardo; Brito-Brito, ZabdielÍtem Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems(ITESO, 2024-02) Dávila-Velarde, René S.; Longoria-Gandara, Omar H.Ítem BLE power measurements on commercial boards(ITESO, 2019-06) Pegueros-Lepe, Ioseth I.; Longoria-Gándara, OmarÍtem Compute Express Link Optimization for Low Latency(ITESO, 2024-05) Baltazar-Ortiz, Ángel A.; Rangel-Patiño, Franciso E.This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.Ítem Diseño de filtro rechaza banda y cálculo de Antipad para un PCB de alta velocidad(ITESO, 2019-08) DeLaTorre-Aguirre, Jaime; Chávez-Hurtado, José L.Ítem En la modalidad: Formación complementaria y proyectos de impacto en un área de concentración(ITESO, 2017-08) Garibay-Garibay, Carlos A.; Chávez-Hurtado, José L.Ítem Estudio del mejoramiento de la resistencia mecánica de la soldadura de un LED de alta potencia(ITESO, 2018-10) Marín-Hernández, Héctor R.; Rizo-Domínguez, LuisÍtem Estudio para mejorar la identificación de problemas de software(ITESO, 2021-05) Zamora-Cortés, Miguel J.; Rizo-Domínguez, LuisÍtem Formación complementaria en área de concentración de diseño de circuitos integrados analógicos(ITESO, 2015-07) Guzmán-Rosales, Gustavo; Brito-Brito, Zabdiel; Martínez-Guerrero, Esteban; Padilla-Cantoya, IvánÍtem Formación técnica complementaria y proyectos de impacto. Diseño electrónico en alta frecuencia(ITESO, 2016-01) Moreyra-González, Rogelio A.; Rayas-Sánchez, José E.Ítem Graphical framework for automatic generation of custom UVM testbenches in SystemVerilog applied for the validation of a SerDes DUT(ITESO, 2021-02) Rivas-Villegas, Rogelio; Limones-Mora, César F.; Salim-Maza, Manuel; Moreno-Reyes, Jesús A.Ítem Guidelines for Building Hybrid Applications Based on Bluetooth Low Energy and IEEE 802.15.4 Protocols(ITESO, 2016-12) Reyes-Chaidez, José M.; Pardiñas-Mir, Jorge A.Ítem High-Frequency Electronic Design Optimization Using Simulated Annealing(ITESO, 2017-11) Alejos-Jiménez, Jesús R.; Rayas-Sánchez, José E.Ítem Improving Harmonic Balance Performance via Parallelization(ITESO, 2016-09) García-BedoyTorres, Jorge; Rayas-Sánchez, José E.Ítem Integration of Transistor Aging Models across Different EDA Environments(ITESO, 2019-09) Velarde-González, Fabio A.Ítem Low-Cost CAN Protocol Logic Analyzer(ITESO, 2021-09) Robles-Martinez, César C.; Pizano-Escalante, José L.Ítem Matlab Driver for Design Parameterization and Optimization of Microstrip Circuits in PowerSI(ITESO, 2019-09) Cabrera-Gómez, Marisol; Rayas-Sánchez, José E.Ítem Mitigating Impedance Matching Disturbances of a Long-Range Wireless Transceiver with Classical Optimization Methods(ITESO, 2021-12) Coria-Pérez, Natalia; DelRey-Acuña, Juan R.