DESI - Trabajos de fin de Maestría en Diseño Electrónico
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Ítem A Practical Start with Zephyr RTOS(ITESO, 2024-12) Ramírez-Sánchez, Earl O.; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.The field of embedded systems has grown significantly in recent years, driving increased demand for advanced Real-Time Operating Systems (RTOS). These systems manage complex tasks, ensure fast responses, and optimize resource usage. Zephyr RTOS stands out as an open-source solution with solid community support and compatibility across various hardware platforms. Supported by the Linux Foundation, its modular design makes it an appealing choice for scalable and customizable solutions. However, new users often face challenges when configuring it for hardware that lacks native support, especially when working with Devicetree structures and Kconfig files. While powerful, these components require a solid understanding of system configuration and hardware integration. This case study provides a practical guide to reduce the learning curve and help developers adapt Zephyr to their projects. It covers critical topics such as adding hardware support for the NXP FRDM-K66F board and a Liquid Crystal Display (LCD) with the PCD8544 controller, handling interrupts, managing multithreading and synchronization, and integrating external devices.Ítem Adaptive Function Segmentation Methodology for Resources Optimization of Hardware-Based Function Evaluators(ITESO, 2017-02) Trejo-Arellano, Juan M.; Longoria-Gándara, Omar H.; Vázquez-Castillo, JavierÍtem Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques(ITESO, 2021-02) Mercado-Casillas, Benjamín; Rayas-Sánchez, José E.Ítem Antenna Design Optimization Through Input Space Mapping(ITESO, 2020-05) Michel-Camacho, Eduardo; Brito-Brito, ZabdielÍtem Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems(ITESO, 2024-02) Dávila-Velarde, René S.; Longoria-Gándara, Omar H.Ítem Availability under threat - CXL Type 3 Vulnerability Assessment(ITESO, 2024-07) Vite-López, Erick E.; Gradilla-Negrete, Ramón E.The growing demand for data processing, driven by technologies such as artificial intelligence, has led the industry to seek more efficient solutions. The Compute Express Link (CXL) protocol stands out as a promising option, offering high-speed, low-latency interconnections between the CPU and other devices, thereby improving resource management, and facilitating the scaling of data-intensive applications. A case study of how the availability of a system could be compromised through a DoS attack targeting the CXL protocol is presented. The context of this work is based on a controlled, secure, and dedicated environment for this research. At no point is a real system/server compromised, and the study is based on the Next Generation Intel® Xeon Server CPU and a CXL type 3 test card. Established in 2019 and publishing the first official specification of the CXL protocol, called CXL 1.0, in March 2020, The CXL Consortium is an open industry standards group established to create technical specifications that enable groundbreaking performance for new usage models, while also supporting an open ecosystem for data center accelerators and other high-speed enhancements. Considering that the protocol is relatively young compared to other protocols, such as PCIe (Peripheral Component Interconnect Express), the "threat modeling" methodology will be followed to identify vulnerabilities that could potentially compromise the system's availability.Ítem BLE power measurements on commercial boards(ITESO, 2019-06) Pegueros-Lepe, Ioseth I.; Longoria-Gándara, Omar H.Ítem Compute Express Link Optimization for Low Latency(ITESO, 2024-05) Baltazar-Ortiz, Ángel A.; Rangel-Patiño, Franciso E.This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.Ítem Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology(ITESO, 2024-11) Jiménez-González, Mario A.; Martínez-Guerrero, Esteban; Aguilera-Galicia, Cuauhtémoc R.This thesis presents a 12-bit ΣΔ ADC design on 45 nm CMOS technology for MEMS sensor applications. The design was performed using Virtuoso Cadence tools. The circuit is composed by a first-order ΣΔ Modulator, a CIC filter, and a Decimator. The first-order ΣΔ Modulator having an oversampling ratio K=128 is developed implementing the switched-capacitor technique. The first-order ΣΔ Modulator is composed by an integrator, a comparator, and a 1-bit DAC. Simulation results show how the Modulator changes the output transitions frequency depending on the input voltage value, being K=128 the best tradeoff between the number of modulations and circuit complexity. The physical design of this block is fully customized. For the digital filter and decimator blocks, a third-order Cascaded Integrator Comb (CIC) filter is developed as a Verilog macro model to test and measure the transient and spectral response of the ADC, as well as its main Figures of Merit.Ítem Diseño de filtro rechaza banda y cálculo de Antipad para un PCB de alta velocidad(ITESO, 2019-08) DeLaTorre-Aguirre, Jaime; Chávez-Hurtado, José L.Ítem Diseño e implementación del curso de Fundamentos de microprocesadores y microcontroladores(ITESO, 2025-02) Sinsel-Duarte, Martín A.; Longoria-Gándara, Omar H.Esta tesis presenta el proceso de diseño e implementación del curso de Fundamentos de Microprocesadores y Microcontroladores que ofrece el Instituto Tecnológico y de Estudios Superiores de Occidente a partir de agosto de 2023. Este curso atiende a los procesos de mejora continua que requiere el Consejo de Acreditación de Enseñanza de la Ingeniería (CACEI), y se ofrece como curso obligatorio para las carreras de Ingeniería en Electrónica, Ingeniería en Sistemas Digitales Embebidos e Ingeniería en Mecatrónica. El proceso implicó una revisión del uso de los microcontroladores en la academia, a nivel licenciatura, y su vínculo con la industria. Así mismo se analizaron algunas de las estrategias didácticas utilizadas para enseñar estas tecnologías a nivel universitario. A lo largo del documento, se desglosa la propuesta del curso en los elementos constitutivos de la guía de aprendizaje, y se presentan los materiales didácticos elaborados, programas de ejemplo y las actividades de aprendizaje, orientados a lograr los objetivos del curso.Ítem En la modalidad: Formación complementaria y proyectos de impacto en un área de concentración(ITESO, 2017-08) Garibay-Garibay, Carlos A.; Chávez-Hurtado, José L.Ítem Estudio del mejoramiento de la resistencia mecánica de la soldadura de un LED de alta potencia(ITESO, 2018-10) Marín-Hernández, Héctor R.; Rizo-Domínguez, LuisÍtem Estudio para mejorar la identificación de problemas de software(ITESO, 2021-05) Zamora-Cortés, Miguel J.; Rizo-Domínguez, LuisÍtem Formación complementaria en área de concentración de diseño de circuitos integrados analógicos(ITESO, 2015-07) Guzmán-Rosales, Gustavo; Brito-Brito, Zabdiel; Martínez-Guerrero, Esteban; Padilla-Cantoya, IvánÍtem Formación técnica complementaria y proyectos de impacto. Diseño electrónico en alta frecuencia(ITESO, 2016-01) Moreyra-González, Rogelio A.; Rayas-Sánchez, José E.Ítem Graphical framework for automatic generation of custom UVM testbenches in SystemVerilog applied for the validation of a SerDes DUT(ITESO, 2021-02) Rivas-Villegas, Rogelio; Limones-Mora, César F.; Salim-Maza, Manuel; Moreno-Reyes, Jesús A.Ítem Guidelines for Building Hybrid Applications Based on Bluetooth Low Energy and IEEE 802.15.4 Protocols(ITESO, 2016-12) Reyes-Chaidez, José M.; Pardiñas-Mir, Jorge A.Ítem High-Frequency Electronic Design Optimization Using Simulated Annealing(ITESO, 2017-11) Alejos-Jiménez, Jesús R.; Rayas-Sánchez, José E.Ítem Improving Harmonic Balance Performance via Parallelization(ITESO, 2016-09) García-BedoyTorres, Jorge; Rayas-Sánchez, José E.