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Design, Implementation and Verification of a Deserializer Module for a SerDes Mixed Signal System on Chip in 130 nm CMOS Technology

Rivas-Villegas, Rogelio (ITESO, 2016-08)

A predictive control unit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications

Moreno-Contreras, Mario A. (ITESO, 2020-10)

Diseño de recuperador de datos y reloj adaptivo a jitter

García-Hernández, Néstor D. (ITESO, 2018-08)

Voltaje de referencia BandGap y módulo de comunicación serial para SAR ADC 10 bits de baja potencia para aplicaciones biomédicas

González-Ornelas, Luis A. (ITESO, 2021-10)

Serializer Design for a SerDes chip in 130nm CMOS Technology

Arrambide-Barrón, Efraín (ITESO, 2016-08)

Diseño e implementación del módulo analógico de recepción para un SerDes en tecnología CMOS de 130nm

Toledo-Ojeda, Oscar (ITESO, 2017-11)

Test Modules Design for a SerDes Chip in 130 nm CMOS technology

Limones-Mora, César F. (ITESO, 2016-07)

Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology

Figueroa-Vázquez, Cristian F. (ITESO, 2020-08)

Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology

Hernández-Flores, Jaime G. (ITESO, 2020-08)

Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology

Conde-Almada, Ernesto (ITESO, 2016-07)

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