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Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology

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dc.contributor.author Conde-Almada, Ernesto
dc.date.accessioned 2016-09-06T18:28:01Z
dc.date.available 2016-09-06T18:28:01Z
dc.date.issued 2016-07
dc.identifier.citation Conde-Almada, E. (2016). Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. es
dc.identifier.uri http://hdl.handle.net/11117/3848
dc.description An analog receiver module for a SerDes with a data rate of 2.5 Gbps for PCI Express Gen 1, is presented. The module is composed by a high-speed differential amplifier, a replica bias circuit and a CML to CMOS converter with duty-cycle correction. The circuit was designed in CMOS 130nm process technology with a supply voltage of 1.2V. A high gain amplifier using the selfcascode technique allows to overcome the low output impedance limitation set by the 130nm technology. Simulation results show no functional issues under PVT corners and mismatch conditions, accomplishing PCI Express Gen 1 specifications. es
dc.description.sponsorship Consejo Nacional de Ciencia y Tecnología es
dc.language.iso eng es
dc.publisher ITESO es
dc.rights.uri http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf es
dc.subject Analog es
dc.subject Receiver es
dc.subject PCI Express es
dc.subject SerDes es
dc.subject High-Speed I es
dc.subject O’s es
dc.subject Duty Cycle Correction es
dc.subject CML es
dc.subject IC Design es
dc.title Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology es
dc.type info:eu-repo/semantics/academicSpecialization es
dc.contributor.director Martínez-Guerrero, Esteban
dc.contributor.director Juárez-Hernández, Esdras
rei.peerreviewed Yes es


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