ReI

Repositorio Institucional del ITESO

Test Modules Design for a SerDes Chip in 130 nm CMOS technology

Manakin: DSpace XMLUI Project v2

Mostrar el registro sencillo del ítem

dc.contributor.author Limones-Mora, César F.
dc.date.accessioned 2016-09-23T15:28:48Z
dc.date.available 2016-09-23T15:28:48Z
dc.date.issued 2016-07
dc.identifier.citation Limones-Mora, C. F. (2016). Test Modules Design for a SerDes Chip in 130 nm CMOS technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO es
dc.identifier.uri http://hdl.handle.net/11117/3892
dc.description In this thesis, a DFT architecture is proposed for testing a high-speed SerDes circuit. This architecture suggests the implementation of three testing modules: a comparator, a linear-feedback shift register (LFSR) and a signal driver. By embedding these test modules to the SerDes, the circuit will be able to perform eight different operating modes for testing in addition to the functional mode. With these operating modes, the functionality of all the modules individually and collectively can be tested by the use of multiplexers and BIST. es
dc.description.sponsorship Consejo Nacional de Ciencia y Tecnología es
dc.language.iso eng es
dc.publisher ITESO es
dc.rights.uri http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf es
dc.subject DFT es
dc.subject Serializer es
dc.subject Deserializer es
dc.subject LFSR es
dc.subject SerDes es
dc.subject 130nm es
dc.subject CMOS es
dc.subject Comparator es
dc.subject RTL es
dc.subject Test Modules es
dc.title Test Modules Design for a SerDes Chip in 130 nm CMOS technology es
dc.type info:eu-repo/semantics/academicSpecialization es
dc.contributor.director Girón-Allende, Alexandro
dc.contributor.director Avedaño-Fernández, Víctor
rei.peerreviewed Yes es


Archivos en el ítem

Este ítem aparece en la(s) siguiente(s) colección(ones)

Mostrar el registro sencillo del ítem

Buscar en todo


Listar

Mi cuenta