| dc.contributor.author | Rivas-Villegas, Rogelio | |
| dc.date.accessioned | 2016-11-02T15:02:56Z | |
| dc.date.available | 2016-11-02T15:02:56Z | |
| dc.date.issued | 2016-08 | |
| dc.identifier.citation | Rivas-Villegas, R. (2016). Design, Implementation and Verification of a Deserializer Module for a SerDes Mixed Signal System on Chip in 130 nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO. | es |
| dc.identifier.uri | http://hdl.handle.net/11117/3990 | |
| dc.description | This document presents the design, verification and physical implementation process of a digital receiver of a mixed signal System on Chip called SerDes. This circuit consists in a communication system based on the P
CI Express standard. The ITESO TV2 project walks through the full logic and physical design of an integrated circuit, starting from the specs definitions to the generation of the output files that are delivered to the MOSIS manufacturing team. A detailed description of the digital deserializer and decoding microarchitecture is presented, followed by the physical layout equivalent circuit implementation. | es |
| dc.description.sponsorship | Consejo Nacional de Ciencia y Tecnología | es |
| dc.language.iso | eng | es |
| dc.publisher | ITESO | es |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es |
| dc.subject | SerDes | es |
| dc.subject | Digital Receiver | es |
| dc.subject | Communication System | es |
| dc.title | Design, Implementation and Verification of a Deserializer Module for a SerDes Mixed Signal System on Chip in 130 nm CMOS Technology | es |
| dc.type | info:eu-repo/semantics/academicSpecialization | es |
| dc.contributor.director | Aguilera-Galicia, Cuauhtémoc R. | |
| dc.contributor.director | Avedaño-Fernández, Víctor | |
| rei.peerreviewed | Yes | es |
