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Machine learning techniques and space mapping approaches to enhance signal and power integrity in high-speed links and power delivery networks

Rayas-Sánchez, José E.; Rangel-Patiño, Francisco E.; Mercado-Casillas, Benjamin; Leal-Romo, Felipe; Chávez-Hurtado, José L. (IEEE, 2020-02-26)

Fast jitter tolerance testing for high-speed serial links in post-silicon validation

Viveros-Wacher, Andrés; Baca-Baylón, Ricardo; Silva-Cortés, Johana L.; Vega-Ochoa, Edgar A.; Rayas-Sánchez, José E.; Rangel-Patiño, Francisco E. (IEEE, 2021-11)

Transmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4

Ruiz-Urbina, Roberto J.; Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Vega-Ochoa, Édgar A.; Longoria-Gándara, Omar (IEEE, 2021-05)

A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

Rangel-Patiño, Francisco E.; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Duron-Rosales, Ismael; Vega-Ochoa, Édgar A.; Hakim, Nagib; López-Miralrio, Enrique (IEEE, 2020-06)

Surrogate-based modeling and design optimization techniques for signal integrity in high-performance computer platforms

Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E. (World Scientific Publishing Europe, 2022-04)