| dc.contributor.author | Rangel-Patiño, Francisco E. | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.date.accessioned | 2022-05-13T00:11:58Z | |
| dc.date.available | 2022-05-13T00:11:58Z | |
| dc.date.issued | 2022-04 | |
| dc.identifier.citation | F. E. Rangel-Patiño and J. E. Rayas-Sánchez, “Surrogate-based modeling and design optimization techniques for signal integrity in high-performance computer platforms,” in Surrogate Modeling for High-Frequency Design: Recent Advances, S. Koziel and A. Pietrenko-Dabrowska, Ed., Singapore: World Scientific Pub. Europe, 2022, ch. 5, pp. 153-211. | es_MX |
| dc.identifier.isbn | 978-1-80061-074-3 | |
| dc.identifier.uri | https://hdl.handle.net/11117/7988 | |
| dc.description | As microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over different process, voltage, and temperature (PVT) conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors; many of them employed in high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in post-silicon electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired signal integrity effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this chapter, dedicated surrogate-based modeling and optimization methods, including space mapping, are described to efficiently tune transmitter and receiver equalizers of HSIO links. The proposed methodologies are validated by laboratory measurements on realistic industrial post-silicon validation platforms. | es_MX |
| dc.description.sponsorship | ITESO, A.C. | es |
| dc.language.iso | eng | es_MX |
| dc.publisher | World Scientific Publishing Europe | es_MX |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | es_MX |
| dc.subject | Equalization | es_MX |
| dc.subject | Eye Diagram | en |
| dc.subject | High-speed Links | en |
| dc.subject | Jitter | en |
| dc.subject | Kriging | en |
| dc.subject | Neural Networks | en |
| dc.subject | Orthogonal Arrays | en |
| dc.subject | Physical Layer Tuning | en |
| dc.subject | Post-silicon Validation | en |
| dc.subject | SATA | en |
| dc.subject | Space Mapping | en |
| dc.subject | Sobol | en |
| dc.subject | Support Vector Machines | en |
| dc.subject | Surrogate-based Optimization | en |
| dc.subject | System Margining | en |
| dc.subject | USB | en |
| dc.title | Surrogate-based modeling and design optimization techniques for signal integrity in high-performance computer platforms | es_MX |
| dc.type | info:eu-repo/semantics/bookPart | es_MX |
| dc.type.version | info:eu-repo/semantics/publishedVersion | es_MX |
