2024-03-29T15:25:43Zhttps://rei.iteso.mx/oai/requestoai:rei.iteso.mx:11117/63912021-10-27T05:00:00Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Aguilera-Galicia, Cuauhtemoc R.
author
Moreno-Contreras, Mario A.
2020-11-10T20:49:18Z
2020-11-10T20:49:18Z
2020-10
Moreno-Contreras, M. A. (2020). A predictive control unit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6391
eng
Analog to Digital Converter
Predictive Algorithm
A predictive control unit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications
info:eu-repo/semantics/academicSpecialization
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YmllcmUgY29uZHVjaWRvIGNvbiB2ZXJkYWQgYSBsYSBmaXJtYSBkZWwgcHJlc2VudGUgCglkb2N1bWVudG87IG5vIHNlYSBlbCB0aXR1bGFyIGRlIGxvcyBEZXJlY2hvcyBkZSBBdXRvcjsgbm8gaGF5YSAKCW9idGVuaWRvIGxhIGF1dG9yaXphY2nDs24gbmVjZXNhcmlhIGVuIGNhc28gZGUgcXVlIGh1YmllcmVuIG90cm9zIAoJYXV0b3JlcywgcGF0cm9jaW5hZG9yZXMsIGZpbmFuY2lhZG9yZXMgbyBlZGl0b3JlcyBwYXJhIHBvZGVyIGRpc3BvbmVyIAoJZGUgbGEgT2JyYSBlbiBsYSBmb3JtYSBlbiBxdWUgc2Ugc2XDsWFsYSBlbiBlc3RlIGRvY3VtZW50bywgbyBubyBoYXlhIAoJdGVuaWRvIGVsIGRlcmVjaG8gcGFyYSBmaXJtYXIgZWwgcHJlc2VudGUgZG9jdW1lbnRvIHBvciBjdWFscXVpZXIgCgljYXVzYSBvIHJhesOzbi4gU2UgZW50aWVuZGUgcXVlIEVsIExpY2VuY2lhdGFyaW8gb2JyYSBlbiB0b2RvIG1vbWVudG8gCglkZSBidWVuYSBmZS4KCgkyLi0gRWwgTGljZW5jaWFudGUgZW50aWVuZGUgcXVlIHVuYSB2ZXogcXVlIGVsIHRyYWJham8gZXMgZGVwb3NpdGFkbyAKCWVuIGVsIFJlcG9zaXRvcmlvLCB1bmEgY2l0YSBiaWJsaW9ncsOhZmljYSBjb21wbGV0YSBkZWwgdHJhYmFqbyBzZXLDoSAKCXZpc2libGUgYSBwZXJwZXR1aWRhZCwgaW5jbHVzbyBzaSBlbCB0cmFiYWpvIGVzIHJlbW92aWRvIG8gZGFkbyBkZSAKCWJhamEuIAoKCTMuLSBFbCBSZXBvc2l0b3JpbyBpZGVudGlmaWNhcsOhIGNsYXJhbWVudGUgcXVlIHVzdGVkIGVzIGVsIGF1dG9yIG8gCgljb2F1dG9yIGRlbCBkb2N1bWVudG8gaW5jbHVpZG8geSBubyBhbHRlcmFyw6EgbmFkYSBkZWwgY29udGVuaWRvIHF1ZSAKCW5vIGVzdMOpIHBlcm1pdGlkbyBwb3IgZXN0YSBsaWNlbmNpYS4KCgk0Li0gRWwgTGljZW5jaWF0YXJpbyBwb2Ryw6EgcmVtb3ZlciBsYSBvYnJhIGVuIGN1YWxxdWllciBtb21lbnRvIHBvciAKCXJhem9uZXMgYWRtaW5pc3RyYXRpdmFzLCBvIGVuIGVsIGNhc28gZGUgdW5hIGV2ZW50dWFsIGRpc3B1dGEgbGVnYWwgCglwb3IgcG9zaWJsZSB2aW9sYWNpw7NuIGEgbG9zIERlcmVjaG9zIGRlIEF1dG9yLgoKTGXDrWRvIHF1ZSBmdWUgZWwgcHJlc2VudGUgZG9jdW1lbnRvLCBleHByZXNhbmRvIHN1IGNvbmZvcm1pZGFkIGNvbiBlbCAKY29udGVuaWRvLCB5IHF1ZSBlbiBlbCBtaXNtbyBubyBleGlzdGnDsyBkb2xvLCBlcnJvciBvIG1hbGEgZmUsIGxvIGZpcm1hIGVuIApUbGFxdWVwYXF1ZSwgSmFsaXNjbywgZWwgZMOtYSBUaHUgTm92IDA1IDExOjI4OjE2IENTVCAyMDIwLgoKRUwgTElDRU5DSUFOVEUgCgpNQVJJTyBBTEJFUlRPIE1PUkVOTyBDT05UUkVSQVMKCkZJUk1PIERFIENPTkZPUk1JREFEIFkgQkFKTyBQUk9URVNUQSBERSBDT05EVUNJUk1FIENPTiBWRVJEQUQKCg==
URL
https://rei.iteso.mx/bitstream/11117/6391/1/A%20predictive%20control%20unit%20for%e2%80%afa%e2%80%afLow%20Power%2010-bit%e2%80%af200kS%20SAR%20ADC%20with%20Adaptive%20Conversion%20Cycle%20oriented%20to%20Audio%20Applications.pdf
File
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application/pdf
A predictive control unit for a Low Power 10-bit 200kS SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications.pdf
URL
https://rei.iteso.mx/bitstream/11117/6391/3/A%20predictive%20control%20unit%20for%e2%80%afa%e2%80%afLow%20Power%2010-bit%e2%80%af200kS%20SAR%20ADC%20with%20Adaptive%20Conversion%20Cycle%20oriented%20to%20Audio%20Applications.pdf.txt
File
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text/plain
A predictive control unit for a Low Power 10-bit 200kS SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications.pdf.txt
oai:rei.iteso.mx:11117/57182020-02-12T06:45:35Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
García-Hernández, Néstor D.
director
Salim-Maza, Manuel
director
Avendaño-Fernández, Víctor
2018-11-29T19:50:52Z
2018-11-29T19:50:52Z
2018-08
García-Hernández, N. D. (2018). Diseño de recuperador de datos y reloj adaptivo a jitter. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5718
spa
CDR
BiCMOS
Tecnología 130nm
EDI Encounter
Verilog
Virtuoso Cadence
VLSI
Recuperación de Datos
Sistemas en Chip
Adaptivo a Jitter
Diseño de recuperador de datos y reloj adaptivo a jitter
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5718/2/Recuperador_de_datos_y_reloj_adaptivo_a_jitter.pdf
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oai:rei.iteso.mx:11117/76192021-10-30T03:00:42Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Chávez-Hurtado, Jose L.
advisor
Martínez-Guerrero, Esteban
advisor
Aguilera-Galicia, Cuauhtémoc R.
author
González-Ornelas, Luis A.
2021-10-30T00:32:27Z
2021-10-30T00:32:27Z
2021-10
González-Ornelas, L. A. (2021). Voltaje de referencia BandGap y módulo de comunicación serial para SAR ADC 10 bits de baja potencia para aplicaciones biomédicas. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/7619
eng
Digital to Analog Converter
Voltaje de referencia BandGap y módulo de comunicación serial para SAR ADC 10 bits de baja potencia para aplicaciones biomédicas
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/7619/3/EDSEC_ToG_Luis_Angel_Gonzalez_Ornelas.pdf
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oai:rei.iteso.mx:11117/38502020-02-12T06:50:18Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Arrambide-Barrón, Efraín
director
Avendaño-Fernández, Víctor
director
Aguilera-Galicia, Cuauhtémoc R.
2016-09-08T15:45:48Z
2016-09-08T15:45:48Z
2016-08
Arrambide-Barrón, E. (2016). Serializer Design for a SerDes chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3850
eng
SerDes
PCI Express
Serializer Architecture
Verilog
Serializer Design for a SerDes chip in 130nm CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3850/7/TOG%20Efrain_Arrambide.pdf
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2017383
application/pdf
TOG Efrain_Arrambide.pdf
URL
https://rei.iteso.mx/bitstream/11117/3850/8/TOG%20Efrain_Arrambide.pdf.txt
File
MD5
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87256
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TOG Efrain_Arrambide.pdf.txt
oai:rei.iteso.mx:11117/51392020-02-12T06:45:23Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Toledo-Ojeda, Oscar
director
Padilla-Cantoya, Iván
2018-01-04T19:02:28Z
2018-01-04T19:02:28Z
2017-11
Toledo-Ojeda, O. (2017). Diseño e implementación del módulo analógico de recepción para un SerDes en tecnología CMOS de 130nm. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5139
spa
Receptor Analógico
SerDes
Diseño e implementación del módulo analógico de recepción para un SerDes en tecnología CMOS de 130nm
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5139/2/Dise%c3%b1o%20e%20implementaci%c3%b3n%20del%20m%c3%b3dulo%20anal%c3%b3gico%20de%20recepci%c3%b3n%20para%20un%20SerDes%20en%20tecnolog%c3%ada%20CMOS%20de%20130nm.pdf
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application/pdf
Diseño e implementación del módulo analógico de recepción para un SerDes en tecnología CMOS de 130nm.pdf
URL
https://rei.iteso.mx/bitstream/11117/5139/3/Dise%c3%b1o%20e%20implementaci%c3%b3n%20del%20m%c3%b3dulo%20anal%c3%b3gico%20de%20recepci%c3%b3n%20para%20un%20SerDes%20en%20tecnolog%c3%ada%20CMOS%20de%20130nm.pdf.txt
File
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text/plain
Diseño e implementación del módulo analógico de recepción para un SerDes en tecnología CMOS de 130nm.pdf.txt
oai:rei.iteso.mx:11117/63872021-09-06T16:01:24Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
author
Hernández-Flores, Jaime G.
2020-11-05T21:26:11Z
2020-11-05T21:26:11Z
2020-08
Hernández-Flores, J. G. (2020). Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6387
eng
Time Amplifier
Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6387/1/Time-Amplifier-ToG-Report.pdf
File
MD5
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application/pdf
Time-Amplifier-ToG-Report.pdf
URL
https://rei.iteso.mx/bitstream/11117/6387/3/Time-Amplifier-ToG-Report.pdf.txt
File
MD5
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Time-Amplifier-ToG-Report.pdf.txt
oai:rei.iteso.mx:11117/38922020-02-12T06:50:18Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Limones-Mora, César F.
director
Girón-Allende, Alexandro
director
Avedaño-Fernández, Víctor
2016-09-23T15:28:48Z
2016-09-23T15:28:48Z
2016-07
Limones-Mora, C. F. (2016). Test Modules Design for a SerDes Chip in 130 nm CMOS technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO
http://hdl.handle.net/11117/3892
eng
DFT
Serializer
Deserializer
LFSR
SerDes
130nm
CMOS
Comparator
RTL
Test Modules
Test Modules Design for a SerDes Chip in 130 nm CMOS technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3892/2/TOG%20Cesar%20Limones.pdf
File
MD5
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application/pdf
TOG Cesar Limones.pdf
URL
https://rei.iteso.mx/bitstream/11117/3892/3/TOG%20Cesar%20Limones.pdf.txt
File
MD5
6dca671ec199f6cd7e9a7fa378d552e8
192896
text/plain
TOG Cesar Limones.pdf.txt
oai:rei.iteso.mx:11117/63842021-09-06T15:50:13Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Aguilera-Galicia, Cuauhtémoc R.
author
Figueroa-Vázquez, Cristian F.
2020-11-04T14:59:40Z
2020-11-04T14:59:40Z
2020-08
Figueroa-Vázquez, C. F. (2020). Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6384
eng
Voltage-to-Time Converter
Analog to Digital Converter
Successive Approximation Register
Digital to Analog Converter
Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6384/1/Voltage-To-Time-Converter-ToG-Report_200808.pdf
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Voltage-To-Time-Converter-ToG-Report_200808.pdf
URL
https://rei.iteso.mx/bitstream/11117/6384/3/Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
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text/plain
Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
oai:rei.iteso.mx:11117/39902020-02-12T06:50:18Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Rivas-Villegas, Rogelio
director
Aguilera-Galicia, Cuauhtémoc R.
director
Avedaño-Fernández, Víctor
2016-11-02T15:02:56Z
2016-11-02T15:02:56Z
2016-08
Rivas-Villegas, R. (2016). Design, Implementation and Verification of a Deserializer Module for a SerDes Mixed Signal System on Chip in 130 nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3990
eng
SerDes
Digital Receiver
Communication System
Design, Implementation and Verification of a Deserializer Module for a SerDes Mixed Signal System on Chip in 130 nm CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3990/2/Tesina_V1_0_RRV.pdf
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Tesina_V1_0_RRV.pdf
URL
https://rei.iteso.mx/bitstream/11117/3990/3/Tesina_V1_0_RRV.pdf.txt
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Tesina_V1_0_RRV.pdf.txt
oai:rei.iteso.mx:11117/38482020-02-12T06:50:17Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Conde-Almada, Ernesto
director
Martínez-Guerrero, Esteban
director
Juárez-Hernández, Esdras
2016-09-06T18:28:01Z
2016-09-06T18:28:01Z
2016-07
Conde-Almada, E. (2016). Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3848
eng
Analog
Receiver
PCI Express
SerDes
High-Speed I
O’s
Duty Cycle Correction
CML
IC Design
Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology
info:eu-repo/semantics/academicSpecialization
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ZGFkIGEgbGEgZmlybWEgZGVsIHByZXNlbnRlIAoJZG9jdW1lbnRvOyBubyBzZWEgZWwgdGl0dWxhciBkZSBsb3MgRGVyZWNob3MgZGUgQXV0b3I7IG5vIGhheWEgCglvYnRlbmlkbyBsYSBhdXRvcml6YWNpw7NuIG5lY2VzYXJpYSBlbiBjYXNvIGRlIHF1ZSBodWJpZXJlbiBvdHJvcyAKCWF1dG9yZXMsIHBhdHJvY2luYWRvcmVzLCBmaW5hbmNpYWRvcmVzIG8gZWRpdG9yZXMgcGFyYSBwb2RlciBkaXNwb25lciAKCWRlIGxhIE9icmEgZW4gbGEgZm9ybWEgZW4gcXVlIHNlIHNlw7FhbGEgZW4gZXN0ZSBkb2N1bWVudG8sIG8gbm8gaGF5YSAKCXRlbmlkbyBlbCBkZXJlY2hvIHBhcmEgZmlybWFyIGVsIHByZXNlbnRlIGRvY3VtZW50byBwb3IgY3VhbHF1aWVyIAoJY2F1c2EgbyByYXrDs24uIFNlIGVudGllbmRlIHF1ZSBFbCBMaWNlbmNpYXRhcmlvIG9icmEgZW4gdG9kbyBtb21lbnRvIAoJZGUgYnVlbmEgZmUuCgoJMi4tIEVsIExpY2VuY2lhbnRlIGVudGllbmRlIHF1ZSB1bmEgdmV6IHF1ZSBlbCB0cmFiYWpvIGVzIGRlcG9zaXRhZG8gCgllbiBlbCBSZXBvc2l0b3JpbywgdW5hIGNpdGEgYmlibGlvZ3LDoWZpY2EgY29tcGxldGEgZGVsIHRyYWJham8gc2Vyw6EgCgl2aXNpYmxlIGEgcGVycGV0dWlkYWQsIGluY2x1c28gc2kgZWwgdHJhYmFqbyBlcyByZW1vdmlkbyBvIGRhZG8gZGUgCgliYWphLiAKCgkzLi0gRWwgUmVwb3NpdG9yaW8gaWRlbnRpZmljYXLDoSBjbGFyYW1lbnRlIHF1ZSB1c3RlZCBlcyBlbCBhdXRvciBvIAoJY29hdXRvciBkZWwgZG9jdW1lbnRvIGluY2x1aWRvIHkgbm8gYWx0ZXJhcsOhIG5hZGEgZGVsIGNvbnRlbmlkbyBxdWUgCglubyBlc3TDqSBwZXJtaXRpZG8gcG9yIGVzdGEgbGljZW5jaWEuCgoJNC4tIEVsIExpY2VuY2lhdGFyaW8gcG9kcsOhIHJlbW92ZXIgbGEgb2JyYSBlbiBjdWFscXVpZXIgbW9tZW50byBwb3IgCglyYXpvbmVzIGFkbWluaXN0cmF0aXZhcywgbyBlbiBlbCBjYXNvIGRlIHVuYSBldmVudHVhbCBkaXNwdXRhIGxlZ2FsIAoJcG9yIHBvc2libGUgdmlvbGFjacOzbiBhIGxvcyBEZXJlY2hvcyBkZSBBdXRvci4KCkxlw61kbyBxdWUgZnVlIGVsIHByZXNlbnRlIGRvY3VtZW50bywgZXhwcmVzYW5kbyBzdSBjb25mb3JtaWRhZCBjb24gZWwgCmNvbnRlbmlkbywgeSBxdWUgZW4gZWwgbWlzbW8gbm8gZXhpc3Rpw7MgZG9sbywgZXJyb3IgbyBtYWxhIGZlLCBsbyBmaXJtYSBlbiAKVGxhcXVlcGFxdWUsIEphbGlzY28sIGVsIGTDrWEgVHVlIEF1ZyAyMyAxMTozNToxMyBDRFQgMjAxNi4KCkVMIExJQ0VOQ0lBTlRFIAoKRVJORVNUTyBDT05ERSBBTE1BREEKCkZJUk1PIERFIENPTkZPUk1JREFEIFkgQkFKTyBQUk9URVNUQSBERSBDT05EVUNJUk1FIENPTiBWRVJEQUQKCg==
URL
https://rei.iteso.mx/bitstream/11117/3848/3/Design%20and%20Physical%20Implementation%20of%20an%20Analog%20Receiver%20for%20a%20SerDes%20System%20On%20Chip%20in%20130%20nm%20CMOS%20Technology.pdf
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Design and Physical Implementation of an Analog Receiver for a SerDes System On Chip in 130 nm CMOS Technology.pdf
URL
https://rei.iteso.mx/bitstream/11117/3848/4/Design%20and%20Physical%20Implementation%20of%20an%20Analog%20Receiver%20for%20a%20SerDes%20System%20On%20Chip%20in%20130%20nm%20CMOS%20Technology.pdf.txt
File
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97892
text/plain
Design and Physical Implementation of an Analog Receiver for a SerDes System On Chip in 130 nm CMOS Technology.pdf.txt
oai:rei.iteso.mx:11117/37492020-02-12T06:53:09Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
González-Morales, Graciela C.
director
Aguilera-Galicia, Cuauhtémoc R.
director
Girón-Allende, Alexandro
director
Avedaño-Fernández, Víctor
2016-07-07T22:10:02Z
2016-07-07T22:10:02Z
2015-12
González-Morales, G. C. (2015 Diseño de módulo Serializador de un sistema SerDes para protocolo de comunicación PCI Express. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3749
spa
Serializador
SerDes
VLSI
180 NM
Diseño de módulo Serializador de un sistema SerDes para protocolo de comunicación PCI Express
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3749/2/Tesina_EDSECh_GCGM_final.pdf
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Tesina_EDSECh_GCGM_final.pdf
URL
https://rei.iteso.mx/bitstream/11117/3749/3/Tesina_EDSECh_GCGM_final.pdf.txt
File
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Tesina_EDSECh_GCGM_final.pdf.txt
oai:rei.iteso.mx:11117/57852020-02-12T06:45:53Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Nuñez-López, Francisco J.
director
Aguilera-Galicia, Cuauhtémoc R.
2019-01-10T17:45:25Z
2019-01-10T17:45:25Z
2018-07
Núñez-López, Francisco J. Diseño e implementación de divisor de frecuencia e integración del SoC CDR adaptativo a jitter con LFSR para pruebas y PLL interno con tecnología bicmos de 130 nm. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5785
spa
CDR
LFSR
PLL
Integración de SoC
130 nm
Divisor de Frecuencia
Diseño e implementación de divisor de frecuencia e integración del SoC CDR adaptativo a jitter con LFSR para pruebas y PLL interno con tecnología bicmos de 130 nm
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5785/3/Dise%c3%b1o%20e%20implementaci%c3%b3n%20de%20divisor%20de%20frecuencia%20e%20integraci%c3%b3n%20del%20SoC%20CDR%20adaptativo%20a%20jitter%20con%20LFSR%20para%20pruebas%20y%20PLL%20interno%20con%20tecnolog%c3%ada%20bicmos%20de%20130%20nm.pdf
File
MD5
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application/pdf
Diseño e implementación de divisor de frecuencia e integración del SoC CDR adaptativo a jitter con LFSR para pruebas y PLL interno con tecnología bicmos de 130 nm.pdf
URL
https://rei.iteso.mx/bitstream/11117/5785/4/Dise%c3%b1o%20e%20implementaci%c3%b3n%20de%20divisor%20de%20frecuencia%20e%20integraci%c3%b3n%20del%20SoC%20CDR%20adaptativo%20a%20jitter%20con%20LFSR%20para%20pruebas%20y%20PLL%20interno%20con%20tecnolog%c3%ada%20bicmos%20de%20130%20nm.pdf.txt
File
MD5
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231810
text/plain
Diseño e implementación de divisor de frecuencia e integración del SoC CDR adaptativo a jitter con LFSR para pruebas y PLL interno con tecnología bicmos de 130 nm.pdf.txt
oai:rei.iteso.mx:11117/76912022-01-11T03:00:42Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Aguilera-Galicia, Cuauhtémoc R.
author
Garza-Pérez, Raymundo
2022-01-10T21:15:44Z
2022-01-10T21:15:44Z
2021-07
Garza-Pérez, R. (2021). Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/7691
eng
Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/7691/1/TOG_GarzaRaymundo_final_8Dic.pdf
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URL
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TOG_GarzaRaymundo_final_8Dic.pdf.txt
oai:rei.iteso.mx:11117/75562021-11-04T17:36:55Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
advisor
Aguilera-Galicia, Cuauhtémoc R.
advisor
Chávez-Hurtado, José L.
author
Castañeda-Villalpando, Karina
2021-09-29T17:26:34Z
2021-09-29T17:26:34Z
2021-09
Castañeda-Villalpando, K. (2021). Dynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/7556
eng
Dynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical Applications
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/7556/5/TOG_Karina%20Casta%c3%b1eda.pdf
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oai:rei.iteso.mx:11117/63112021-09-06T15:51:45Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
author
Martínez-Flores, Iván
2020-09-17T18:07:10Z
2020-09-17T18:07:10Z
2020-08
Martínez-Flores, I. (2020) A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6311
eng
TSPC
D FF
D Flip Flop
Positive Edge D FF
A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6311/1/TSPC%20D-FF_20200823_Final.pdf
File
MD5
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application/pdf
TSPC D-FF_20200823_Final.pdf
URL
https://rei.iteso.mx/bitstream/11117/6311/3/TSPC%20D-FF_20200823_Final.pdf.txt
File
MD5
770a377382a4e83072141e2458323d41
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TSPC D-FF_20200823_Final.pdf.txt
oai:rei.iteso.mx:11117/63702021-09-06T16:00:43Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
author
Hernández-Flores, Jaime G.
2020-10-14T02:21:50Z
2020-10-14T02:21:50Z
2020-08
Hernández-Flores, J. G. (2020) Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6370
eng
Time Amplifier
Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6370/1/Time-Amplifier-ToG-Report.pdf
File
MD5
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application/pdf
Time-Amplifier-ToG-Report.pdf
URL
https://rei.iteso.mx/bitstream/11117/6370/3/Time-Amplifier-ToG-Report.pdf.txt
File
MD5
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34237
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Time-Amplifier-ToG-Report.pdf.txt
oai:rei.iteso.mx:11117/39922020-02-12T06:50:19Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Núñez-Corona, Joel A.
director
Martínez-Guerrero, Esteban
director
Lobato-López, Federico
2016-11-02T21:31:52Z
2016-11-02T21:31:52Z
2016-07
Núñez-Corona, J. A. (2016). Design of the Analog Transmitter Module in 130 nm CMOS technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3992
eng
Analog Transmitter Module
SerDes
CMOS
130nm
Design of the Analog Transmitter Module in 130 nm CMOS technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3992/2/TOG%20Joel%20Nu%c3%b1ez.pdf
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TOG Joel Nuñez.pdf
URL
https://rei.iteso.mx/bitstream/11117/3992/3/TOG%20Joel%20Nu%c3%b1ez.pdf.txt
File
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TOG Joel Nuñez.pdf.txt
oai:rei.iteso.mx:11117/57652020-02-12T06:46:10Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
González-Avalos, Diego A.
director
Martínez-Guerrero, Esteban
2018-12-18T19:42:55Z
2018-12-18T19:42:55Z
2018-08
González-Avalos, D. A. (2018). Design of bias circuit for charge pump in 130nm BiCMOS technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5765
eng
Bias Circuit
130nm BiCMOS
Charge Pump
Analog Design
PLL
CDR
Design of bias circuit for charge pump in 130nm BiCMOS technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5765/2/Design%20of%20bias%20circuit%20for%20charge%20pump%20in%20130nm%20BiCMOS%20technology.pdf
File
MD5
211d538ddfe1bdf9bc74da406462fefa
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application/pdf
Design of bias circuit for charge pump in 130nm BiCMOS technology.pdf
URL
https://rei.iteso.mx/bitstream/11117/5765/4/Design%20of%20bias%20circuit%20for%20charge%20pump%20in%20130nm%20BiCMOS%20technology.pdf.txt
File
MD5
63e3102975785db8b11ae72349bf1ca0
73808
text/plain
Design of bias circuit for charge pump in 130nm BiCMOS technology.pdf.txt
oai:rei.iteso.mx:11117/63672021-09-06T15:50:55Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
author
Hernández-Flores, Jaime G.
2020-10-14T01:32:57Z
2020-10-14T01:32:57Z
2020-08
Hernández-Flores, J. G. (2020) A 0.18um CMOS Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6367
eng
Time Amplifier
A 0.18um CMOS Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle oriented to Audio Applications
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6367/1/Time-Amplifier-ToG-Report.pdf
File
MD5
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2627119
application/pdf
Time-Amplifier-ToG-Report.pdf
URL
https://rei.iteso.mx/bitstream/11117/6367/3/Time-Amplifier-ToG-Report.pdf.txt
File
MD5
cc8b1e8503735040d8e941708ebd4404
34101
text/plain
Time-Amplifier-ToG-Report.pdf.txt
oai:rei.iteso.mx:11117/51372020-02-12T06:57:08Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Hoil-Loria, Miguel M.
director
Salim-Maza, Manuel
director
Avendaño-Fernández, Víctor
2018-01-03T22:56:53Z
2018-01-03T22:56:53Z
2017-11
Hoil-Loria, M. M. (2017). Design for Testability in a SerDes System. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5137
eng
SerDes
Chip Design
Design for Testability in a SerDes System
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5137/2/Design%20for%20Testability%20in%20a%20SerDes%20System.pdf
File
MD5
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Design for Testability in a SerDes System.pdf
URL
https://rei.iteso.mx/bitstream/11117/5137/3/Design%20for%20Testability%20in%20a%20SerDes%20System.pdf.txt
File
MD5
475f2ef640c8eaabd4b93e242447c0d1
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text/plain
Design for Testability in a SerDes System.pdf.txt
oai:rei.iteso.mx:11117/37462020-02-12T06:50:15Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Gallardo-García, Omar
director
Juárez-Hernández, Esdras
director
Padilla-Cantoya, Iván
2016-07-07T20:59:14Z
2016-07-07T20:59:14Z
2015-12
Gallardo-García, O. (2015). Diseño del path de alta frecuencia del receptor analógico del SerDes ITESOTV1. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3746
spa
SerDes
Core
Receptor Analógico
Diseño del path de alta frecuencia del receptor analógico del SerDes ITESOTV1
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3746/2/Tesina_Receptor%20anal%c3%b3gico%20SerDes-ITESO-TV1.pdf
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application/pdf
Tesina_Receptor analógico SerDes-ITESO-TV1.pdf
URL
https://rei.iteso.mx/bitstream/11117/3746/3/Tesina_Receptor%20anal%c3%b3gico%20SerDes-ITESO-TV1.pdf.txt
File
MD5
63a31d6e2aea62f66014bd236c1e82e0
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text/plain
Tesina_Receptor analógico SerDes-ITESO-TV1.pdf.txt
oai:rei.iteso.mx:11117/51342020-02-12T06:56:29Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Velásquez-Meling, Alex
director
Padilla-Cantoya, Iván
2018-01-03T18:05:34Z
2018-01-03T18:05:34Z
2017-11
Velásquez-Meling, A. (2017). Diseño del transmisor analógico de un sistema SerDes en tecnología de fabricación de 130 nm. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5134
spa
Transmisor Analógico
Sistemas en Chip
SerDes
Diseño del transmisor analógico de un sistema SerDes en tecnología de fabricación de 130 nm
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5134/4/Transmisor_analogico_en_130_nm_final.pdf
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Transmisor_analogico_en_130_nm_final.pdf
URL
https://rei.iteso.mx/bitstream/11117/5134/5/Transmisor_analogico_en_130_nm_final.pdf.txt
File
MD5
957c333f27c2cc8e5a286efe1dd9a83e
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Transmisor_analogico_en_130_nm_final.pdf.txt
oai:rei.iteso.mx:11117/51402020-02-12T06:45:23Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Aparicio-Zuleta, Christian
director
Brennan-Bourdon, Lorena M.
director
Avendaño-Fernández, Víctor
director
Salim, Manuel
2018-01-04T21:35:32Z
2018-01-04T21:35:32Z
2017-11
Aparicio-Zuleta, C. (2017). Digital Serializer Design for a SerDes Chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/5140
eng
Serializador
VLSI
SerDes
Digital Serializer Design for a SerDes Chip in 130nm CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/5140/2/Digital%20Serializer%20Design%20for%20a%20SerDes%20chip%20in%20130nm%20CMOS%20Technology.pdf
File
MD5
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3970749
application/pdf
Digital Serializer Design for a SerDes chip in 130nm CMOS Technology.pdf
URL
https://rei.iteso.mx/bitstream/11117/5140/3/Digital%20Serializer%20Design%20for%20a%20SerDes%20chip%20in%20130nm%20CMOS%20Technology.pdf.txt
File
MD5
5f63b33968fb48617546519aca23995e
107185
text/plain
Digital Serializer Design for a SerDes chip in 130nm CMOS Technology.pdf.txt
oai:rei.iteso.mx:11117/63922021-09-06T16:00:27Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Martínez-Guerrero, Esteban
author
Martínez-Flores, Iván
2020-11-10T21:04:25Z
2020-11-10T21:04:25Z
2020-08
Martínez-Guerrero, E. (2020) Implementing a TSPC D Flip Flop as an Arbiter for a low power 10- bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://hdl.handle.net/11117/6392
eng
TSPC
D FF
D Flip Flop
Implementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6392/1/TSPC%20D-FF_Final.pdf
File
MD5
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1414282
application/pdf
TSPC D-FF_Final.pdf
URL
https://rei.iteso.mx/bitstream/11117/6392/3/TSPC%20D-FF_Final.pdf.txt
File
MD5
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text/plain
TSPC D-FF_Final.pdf.txt
oai:rei.iteso.mx:11117/37872020-02-12T06:50:16Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Godínez-Maldonado, Ricardo
director
Martínez-Guerrero, Esteban
director
Girón-Allende, Alexandro
director
Avedaño-Fernández, Víctor
2016-08-04T17:05:30Z
2016-08-04T17:05:30Z
2015-12
Godínez-Maldonado, R. (2015). Test Module Design for ITESO TV1 SerDes. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3787
eng
SerDes
Module Design
Test Module Design for ITESO TV1 SerDes
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3787/2/Tesina_ESC_RGM.pdf
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Tesina_ESC_RGM.pdf
URL
https://rei.iteso.mx/bitstream/11117/3787/3/Tesina_ESC_RGM.pdf.txt
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Tesina_ESC_RGM.pdf.txt
oai:rei.iteso.mx:11117/61762020-02-14T20:20:21Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Pizano-Escalante, José L.
author
Ramos-Contreras, Ricardo
author
Dávila-Velarde, René S.
2020-02-14T20:11:49Z
2020-02-14T20:11:49Z
2019-08
Ramos-Contreras, R.; Dávila-Velarde, R. S. (2019). Configurable/adaptive digital FIR filter. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
https://rei.iteso.mx/handle/11117/6176
eng
FIR
Filtro Digital
Filtro Adaptativo
Adaptive Filter
Digital Filter
Configurable/adaptive digital FIR filter
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6176/2/Filtro%20digital%20FIR%20adaptativo%20y%20configurable.pdf
File
MD5
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application/pdf
Filtro digital FIR adaptativo y configurable.pdf
URL
https://rei.iteso.mx/bitstream/11117/6176/3/Filtro%20digital%20FIR%20adaptativo%20y%20configurable.pdf.txt
File
MD5
08ee98edfc28fea8f248889e80da5396
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text/plain
Filtro digital FIR adaptativo y configurable.pdf.txt
oai:rei.iteso.mx:11117/63662021-09-06T15:59:14Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Aguilera-Galicia, Cuauhtémoc R.
author
Figueroa-Vázquez, Cristian F.
2020-10-14T01:25:59Z
2020-10-14T01:25:59Z
2020-08
Figueroa-Vázquez, C. F. (2020). Implementing a Highly-linear Voltage-to-time Converter Circuit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Process Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO
https://hdl.handle.net/11117/6366
eng
High-Quality Audio
Voltage to Time Converter
Analog to Digital Converter
Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6366/3/Voltage-To-Time-Converter-ToG-Report_200808.pdf
File
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application/pdf
Voltage-To-Time-Converter-ToG-Report_200808.pdf
URL
https://rei.iteso.mx/bitstream/11117/6366/5/Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
File
MD5
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text/plain
Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
oai:rei.iteso.mx:11117/37512020-02-12T06:45:51Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
López-Félix, Carlos C.
director
Martínez-Guerrero, Esteban
director
Lobato-López, Federico
2016-07-08T18:41:25Z
2016-07-08T18:41:25Z
2015-12
López-Félix, C. C. (2015). Diseño del módulo transmisor serial de datos de sistema SerDes para Protocolo PCI express 1. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3751
spa
SerDes
SSSTT
Layout
180 NM
CMOSS
Diseño del módulo transmisor serial de datos de sistema SerDes para Protocolo PCI express 1
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/3751/2/Tesina%20Carlos%20Lopez%20Rev%20final.pdf
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Tesina Carlos Lopez Rev final.pdf
URL
https://rei.iteso.mx/bitstream/11117/3751/3/Tesina%20Carlos%20Lopez%20Rev%20final.pdf.txt
File
MD5
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Tesina Carlos Lopez Rev final.pdf.txt
oai:rei.iteso.mx:11117/63652021-09-06T15:50:13Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
advisor
Aguilera-Galicia, Cuauhtémoc R.
author
Figueroa-Vázquez, Cristian F.
2020-10-14T01:16:02Z
2020-10-14T01:16:02Z
2020-08
Figueroa-Vázquez, C. F. (2020). A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO
https://hdl.handle.net/11117/6365
eng
Analog to Digital Converter
Voltage to Time Converter
Digital to Analog Converter
A 0.18um CMOS linear Voltage-to-Time Converter for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle Oriented to Audio Applications
info:eu-repo/semantics/academicSpecialization
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URL
https://rei.iteso.mx/bitstream/11117/6365/1/Voltage-To-Time-Converter-ToG-Report_200808.pdf
File
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application/pdf
Voltage-To-Time-Converter-ToG-Report_200808.pdf
URL
https://rei.iteso.mx/bitstream/11117/6365/3/Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
File
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text/plain
Voltage-To-Time-Converter-ToG-Report_200808.pdf.txt
oai:rei.iteso.mx:11117/37472020-02-12T06:50:15Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Núñez-Corona, Saúl A.
director
Juárez-Hernández, Esdras
director
Padilla-Cantoya, Iván
2016-07-07T21:11:21Z
2016-07-07T21:11:21Z
2015-12
Núñez-Corona, S. A. (2015). Diseño de circuito analógico de polarización para sistema SerDes. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3747
spa
SerDes
Diseño de circuito analógico de polarización para sistema SerDes
info:eu-repo/semantics/academicSpecialization
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byBzZWEgZWwgdGl0dWxhciBkZSBsb3MgRGVyZWNob3MgZGUgQXV0b3I7IG5vIGhheWEgCglvYnRlbmlkbyBsYSBhdXRvcml6YWNpw7NuIG5lY2VzYXJpYSBlbiBjYXNvIGRlIHF1ZSBodWJpZXJlbiBvdHJvcyAKCWF1dG9yZXMsIHBhdHJvY2luYWRvcmVzLCBmaW5hbmNpYWRvcmVzIG8gZWRpdG9yZXMgcGFyYSBwb2RlciBkaXNwb25lciAKCWRlIGxhIE9icmEgZW4gbGEgZm9ybWEgZW4gcXVlIHNlIHNlw7FhbGEgZW4gZXN0ZSBkb2N1bWVudG8sIG8gbm8gaGF5YSAKCXRlbmlkbyBlbCBkZXJlY2hvIHBhcmEgZmlybWFyIGVsIHByZXNlbnRlIGRvY3VtZW50byBwb3IgY3VhbHF1aWVyIAoJY2F1c2EgbyByYXrDs24uIFNlIGVudGllbmRlIHF1ZSBFbCBMaWNlbmNpYXRhcmlvIG9icmEgZW4gdG9kbyBtb21lbnRvIAoJZGUgYnVlbmEgZmUuCgoJMi4tIEVsIExpY2VuY2lhbnRlIGVudGllbmRlIHF1ZSB1bmEgdmV6IHF1ZSBlbCB0cmFiYWpvIGVzIGRlcG9zaXRhZG8gCgllbiBlbCBSZXBvc2l0b3JpbywgdW5hIGNpdGEgYmlibGlvZ3LDoWZpY2EgY29tcGxldGEgZGVsIHRyYWJham8gc2Vyw6EgCgl2aXNpYmxlIGEgcGVycGV0dWlkYWQsIGluY2x1c28gc2kgZWwgdHJhYmFqbyBlcyByZW1vdmlkbyBvIGRhZG8gZGUgCgliYWphLiAKCgkzLi0gRWwgUmVwb3NpdG9yaW8gaWRlbnRpZmljYXLDoSBjbGFyYW1lbnRlIHF1ZSB1c3RlZCBlcyBlbCBhdXRvciBvIAoJY29hdXRvciBkZWwgZG9jdW1lbnRvIGluY2x1aWRvIHkgbm8gYWx0ZXJhcsOhIG5hZGEgZGVsIGNvbnRlbmlkbyBxdWUgCglubyBlc3TDqSBwZXJtaXRpZG8gcG9yIGVzdGEgbGljZW5jaWEuCgoJNC4tIEVsIExpY2VuY2lhdGFyaW8gcG9kcsOhIHJlbW92ZXIgbGEgb2JyYSBlbiBjdWFscXVpZXIgbW9tZW50byBwb3IgCglyYXpvbmVzIGFkbWluaXN0cmF0aXZhcywgbyBlbiBlbCBjYXNvIGRlIHVuYSBldmVudHVhbCBkaXNwdXRhIGxlZ2FsIAoJcG9yIHBvc2libGUgdmlvbGFjacOzbiBhIGxvcyBEZXJlY2hvcyBkZSBBdXRvci4KCkxlw61kbyBxdWUgZnVlIGVsIHByZXNlbnRlIGRvY3VtZW50bywgZXhwcmVzYW5kbyBzdSBjb25mb3JtaWRhZCBjb24gZWwgCmNvbnRlbmlkbywgeSBxdWUgZW4gZWwgbWlzbW8gbm8gZXhpc3Rpw7MgZG9sbywgZXJyb3IgbyBtYWxhIGZlLCBsbyBmaXJtYSBlbiAKVGxhcXVlcGFxdWUsIEphbGlzY28sIGVsIGTDrWEgVGh1IEp1bCAwNyAxNDozMDowMyBDRFQgMjAxNi4KCkVMIExJQ0VOQ0lBTlRFIAoKREVQT1NJVE9TIFJFSQoKRklSTU8gREUgQ09ORk9STUlEQUQgWSBCQUpPIFBST1RFU1RBIERFIENPTkRVQ0lSTUUgQ09OIFZFUkRBRAoK
URL
https://rei.iteso.mx/bitstream/11117/3747/2/Dise%c3%b1o%20de%20circuito%20anal%c3%b3gico%20de%20polarizaci%c3%b3n%20para%20sistema%20SerDes%20_EDSECh_Saul%20Alfonso%20NU%c3%b1ez%20Corona.pdf
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application/pdf
Diseño de circuito analógico de polarización para sistema SerDes _EDSECh_Saul Alfonso NUñez Corona.pdf
URL
https://rei.iteso.mx/bitstream/11117/3747/3/Dise%c3%b1o%20de%20circuito%20anal%c3%b3gico%20de%20polarizaci%c3%b3n%20para%20sistema%20SerDes%20_EDSECh_Saul%20Alfonso%20NU%c3%b1ez%20Corona.pdf.txt
File
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text/plain
Diseño de circuito analógico de polarización para sistema SerDes _EDSECh_Saul Alfonso NUñez Corona.pdf.txt
oai:rei.iteso.mx:11117/37502020-02-12T06:50:15Zcom_11117_560col_11117_3427
Repositorio Institucional del ITESO (ReI)
author
Centeno-Quiñonez, José M.
director
Aguilera-Galicia, Cuauhtémoc R.
director
Girón-Allende, Alexandro
director
Avedaño-Fernández, Víctor
2016-07-07T22:12:55Z
2016-07-07T22:12:55Z
2015-12
Centeno-Quiñonez, J. M. (2015). Design and Integration of a Deserializer Module for a SerDes Mixed Signal System on Chip. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.
http://hdl.handle.net/11117/3750
eng
SerDes
Deserializer
SoC
180 NM
VLSI
Design and Integration of a Deserializer Module for a SerDes Mixed Signal System on Chip
info:eu-repo/semantics/academicSpecialization
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