A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications
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Fecha
2020-08
Autores
Martínez-Flores, Iván
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ITESO
Resumen
Descripción
This document presents the design of an arbiter circuit for a time-based SAR-ADC. The arbiter is a TSPC D flip flop. It was designed in TSMC 0.18 μm CMOS technology with 1.8 V supply voltage. It was tested at a clock frequency of 200 KHz, but it can operate even at 100 MHz. Simulation results using the typical process parameters shown a setup time of 5.02 ps and Hold time of 51.72 ps, the TSPC D flip flop power consumption is 62.61 μW@200 KHz, and the layout area is 368.284 μm2.
The simulation is performed across all PVT corners that vary from a temperature of -40 °C up to 125 °C, with a supply voltage variation from 1.62 V up to 1.98 V and the TSPC D flip flop functionality is correct.
Palabras clave
TSPC, D FF, D Flip Flop, Positive Edge D FF
Citación
Martínez-Flores, I. (2020) A 0.18um CMOS TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle Oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.