Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology
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Fecha
2020-08
Autores
Hernández-Flores, Jaime G.
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ITESO
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Descripción
This document presents the design of a time amplifier circuit in 0.18 m CMOS process with a supply voltage of 1.8 V. Simulation results performed with typical process parameters, nominal supply voltage, room temperature and an operating frequency of 200 KHz, show a time gain of 200, with an error of less than 7%. The power consumption of the designed circuit is 26 W. The circuit can receive signals with a time difference from 10 ps to 4.7 nS. The layout dimension is 149.985 m x 168.536 m, with an area of 25.3 nm2.
Palabras clave
Time Amplifier
Citación
Hernández-Flores, J. G. (2020) Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.