Implementing a highly-linear Voltage-to-time converter circuit for a low power 10-bit 200kS/s SAR ADC with Adaptive Conversion cycle for high-quality audio applications in 0.18um TSMC CMOS process technology
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Fecha
2020-08
Autores
Figueroa-Vázquez, Cristian F.
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ITESO
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Descripción
This document presents a 0.18 um CMOS process highly-linear Voltage-to-Time Converter (VTC) design that can operate at a low voltage of 1.8 V across PVT corners and with the power consumption of less than 13 uW and linearity error less than 1%. The VTC was designed to work at a minimum of 1.68 V and accepts a maximum clock frequency of 900 MHz; to reduce non-linear behavior a symmetric load and current starved inverter configuration was proposed. This circuit was designed using TSMC 0.18 um CMOS process technology.
Palabras clave
High-Quality Audio, Voltage to Time Converter, Analog to Digital Converter
Citación
Figueroa-Vázquez, C. F. (2020). Implementing a Highly-linear Voltage-to-time Converter Circuit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Process Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO