PCIe Gen5 Physical Layer Equalization Tuning by Using K-means Clustering and Gaussian Process Regression Modeling in Industrial Post-silicon Validation

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dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorViveros-Wacher, Andres
dc.contributor.authorRajyaguru, Chintan
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorRodriguez-Saenz, Sofia D.
dc.contributor.authorSilva-Cortes, Johana L.
dc.contributor.authorShival, Hemanth
dc.contributor.authorRayas-Sánchez, José E.
dc.date.accessioned2023-08-14T18:41:09Z
dc.date.available2023-08-14T18:41:09Z
dc.date.issued2023-06-30
dc.descriptionPeripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry. The continuously increasing bandwidth demand from new applications has led to the development of the PCIe Gen5, reaching data rates of 32 GT/s. To mitigate undesired channel effects due to such high-speed, the PCIe specification defines an equalization process at the transmitter (Tx) and the receiver (Rx). Current post-silicon validation practices consist of finding an optimal subset of Tx and Rx coefficients by measuring the eye diagrams across different channels. However, these experiments are very time consuming since they require massive lab measurements. In this paper, we use a K-means approach to cluster all available post-silicon data from different channels and feed those clusters to a Gaussian process regression (GPR)-based metamodel for each channel. We then perform a surrogate-based optimization to obtain the optimal tuning settings for the specific channels. Our methodology is validated by measurements of the functional eye diagram of an industrial computer platform.es_MX
dc.description.sponsorshipITESO, A.C.es
dc.identifier.citationF. E. Rangel-Patiño, A. Viveros-Wacher, C. Rajyaguru, E. A. Vega-Ochoa, S. D. Rodriguez-Saenz, J. L. Silva-Cortes, H. Shival, and J. E. Rayas-Sánchez. “PCIe Gen5 physical layer equalization tuning by using K-means clustering and Gaussian process regression modeling in industrial post-silicon validation,” in IEEE MTT-S Int. Conf. Numer. EM Mutiphysics Modeling Opt. (NEMO-2023), Winnipeg, MB, Canada, Jun. 2023, pp. 162-165.es_MX
dc.identifier.isbn979-8-3503-4741-8
dc.identifier.issn2575-4742
dc.identifier.urihttps://hdl.handle.net/11117/9644
dc.language.isoenges_MX
dc.publisherIEEEes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectClusteringes_MX
dc.subjectEqualizationes_MX
dc.subjectEqualization Mapses_MX
dc.subjectEye-diagrames_MX
dc.subjectFIRes_MX
dc.subjectGPRes_MX
dc.subjectHSIOes_MX
dc.subjectHigh-speed Linkses_MX
dc.subjectMetamodelses_MX
dc.subjectOptimizationes_MX
dc.subjectPCIees_MX
dc.subjectPost-silicon Validationes_MX
dc.subjectReceiveres_MX
dc.subjectSignal Integrityes_MX
dc.subjectTransmitteres_MX
dc.subjectTuninges_MX
dc.titlePCIe Gen5 Physical Layer Equalization Tuning by Using K-means Clustering and Gaussian Process Regression Modeling in Industrial Post-silicon Validationes_MX
dc.typeinfo:eu-repo/semantics/articlees_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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