System Margining Surrogate-Based Optimization in Post-Silicon Validation
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Fecha
2017-09
Autores
Rangel-Patiño, Francisco E.
Chávez-Hurtado, José L.
Viveros-Wacher, Andrés
Rayas-Sánchez, José E.
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ISSN de la revista
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Editor
IEEE
Resumen
Descripción
There is an increasingly higher number of mixed-signal circuits within microprocessors. A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links is critical to provide a release qualification decision. One of the major challenges in HSIO electrical validation is the physical layer (PHY) tuning process, where equalization techniques are typically used to cancel any undesired effect. Current industrial practices for PHY tuning in HSIO links are very time consuming since they require massive lab measurements. On the other hand, surrogate modeling techniques allow to develop an approximation of a system response within a design space of interest. In this paper, we analyze several surrogate modeling methods and design of experiments techniques to identify the best approach to efficiently optimize a receiver equalizer. We evaluate the models performance by comparing with actual measured responses on a real server HSIO link. We then perform a surrogate-based optimization on the best model to obtain the optimal PHY tuning settings of a HSIO link. Our methodology is validated by measuring the real functional eye diagram of the physical system using the optimal surrogate model solution.
Palabras clave
DoE, Equalization, Eye Diagram, HSIO, Kriging, Neural Network, Optimization, Post-silicon Validation, Surrogate Models, Receiver, Support Vector Machines
Citación
F. E. Rangel-Patiño, J. L. Chávez-Hurtado, A. Viveros-Wacher, J. E. Rayas-Sánchez, and N. Hakim, “System margining surrogate-based optimization in post-silicon validation,” IEEE Trans. Microwave Theory Techn., vol. 65, no. 9, pp. 3109-3115, Sep. 2017. DOI: 10.1109/TMTT.2017.2701368