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Ítem Cognitive Parameter Extraction for Space Mapping Design Optimization(IEEE, 2025) Rayas-Sánchez, José E.Parameter extraction (PE) is a key subproblem of space mapping (SM) design optimization. It consists of a local alignment between the coarse and fine models at each SM iteration. In this work, cognition-driven PE is proposed for SM. In contrast to classical PE, where the full fine model responses are used as targets, the proposed cognitive PE focuses on key features of the fine model response selected from an engineering perspective. It is demonstrated that the proposed cognitive PE approach: 1) yields more accurate extracted parameters regardless of the type of PE objective function employed; and 2) achieves a more meaningful matching to the fine model target response and with less variability. To proof this with independence of the optimization method employed for PE, plots of the PE objective functions are presented over large regions of the coarse model design space. Two synthetic examples are used to support these findings.Ítem AI-Enhanced Post-Silicon Validation: Tackling Signal Integrity Issues in High-Speed Interconnects(IEEE, 2025-01-23) Rangel-Patiño, Francisco; Vega-Ochoa, Edgar A.; Viveros-Wacher, Andres; Onsongo, Daudi; Rayas-Sánchez, José E.Semiconductor technology advances, coupled with the demand for higher data rates and bandwidth, has led to significant signal integrity issues such as attenuation, crosstalk, jitter, noise, EM susceptibility, etc. Traditional post-silicon validation methods for high-performance computer platforms, which rely heavily on manual inspection and rule-based heuristics, are increasingly inadequate for addressing these complexities. In this paper, we review and highlight the application of artificial intelligence (AI) approaches and machine learning (ML) techniques to automate post-silicon validation and enhance the detection and diagnosis of signal integrity issues in high-speed computer interfaces. Through a series of case studies, we demonstrate the efficacy of various AI techniques, including artificial neural networks (ANNs), surrogate modeling, and unsupervised learning, in optimizing settings and improving the efficiency of post-silicon validation. These techniques significantly reduce the number of required measurements, enhance accuracy, and provide scalable and flexible solutions for modern post-silicon physical layer validation and tuning processes.Ítem A Rigorous Numerical Comparison for Parameter Extraction Using Classical and Kullback-Leibler Formulations Illustrated with Full-Wave EM and Equivalent Circuit Models for Microstrip Filters(IEEE, 2025-01) Loera-Díaz, Roberto; Rayas-Sánchez, José E.; Villa-Loustaunau, Enrique R.Numerical circuit parameter extraction (PE) is a key sub-process of space mapping (SM), which is used to efficiently optimize full-wave EM responses of microwave structures exploiting faster but inaccurate physics-based auxiliary models. Any improvement in PE has a positive impact on SM design optimization. In this paper, we apply for the first time a PE formulation based on the Kullback-Leibler distance to microstrip filters using their full-wave EM responses as targets. We perform a rigorous numerical comparison of PE based on the K-L formulation against PE using classical norms. Our results confirm a better PE performance using the Kullback-Leibler formulation than those obtained with traditional PE formulations.Ítem Optimizing the Full Mixed-Mode Performance of a Differential Microstrip Interconnect with a Right-Angle Bend by using Two Symmetrical Bumps(IEEE, 2025-01) Villa-Loustaunau, Enrique R.; Rayas-Sánchez, José E.; Loera-Díaz, Roberto; Rangel-Patiño, FranciscoDifferential interconnects are widely used for high-speed serial data transmission in modern high-performance computer platforms. Differential signaling handle noise better than single ended signaling. However, physical asymmetries and discontinuities in differential links can cause that a portion of the differential energy is converted into common mode (CM) energy, which is perceived as noise at the receiver. This mode conversion in differential interconnects leads to electromagnetic (EM) interference and EM susceptibility, limiting high data rates. In this paper, a microstrip differential interconnect with a severe discontinuity, a right-angle bend, is optimally compensated by using two rectangular length-match bumps. Our formulation allows the efficient optimization of the full set of mixed-mode (MM) S-parameters of the differential interconnect. It uses a smart combination of pattern search and Nelder-Mead to optimize the MM performance considering several starting points. The interconnect MM performance before and after optimization is shown, confirming a very significant performance improvement.Ítem PCI Express Gen6 FIR Filter Optimization by Space Mapping for Post-Silicon Validation(IEEE, 2025-01) Rangel-Patiño, Francisco; Rayas-Sánchez, José E.; Moreno-Mojica, Aurea E.The evolution of PCI Express technology to Gen6, and the forthcoming Gen7, has markedly increased data transfer speeds, presenting new challenges for signal integrity. To tackle these challenges, advanced design strategies, such as enhanced equalization (EQ) techniques, are necessary. Traditional EQ methods typically involve extensive laboratory measurements, rendering the EQ process highly time intensive. In this paper, we introduce an optimization methodology for the PCIe Gen6 transmitter (Tx) equalizer utilizing the Aggressive Space Mapping (ASM) algorithm. Our ASM approach employs a computationally efficient surrogate as coarse model to estimate eye diagram margins. An implicit mapping between the coarse and fine model equalizer settings is established, leading to an efficient optimization for the EQ tuning process. The effectiveness of the ASM methodology is confirmed through simulations with the MATLAB SerDes Toolbox, resulting in notable enhancements in the eye diagram area and overall system margins.Ítem Microwave Modeling and Design Optimization: The Legacy of John Bandler(IEEE, 2024-08-12) Zhang, Qi-Jun; Rautio, James C.; Nikolova, Natalia K.; Boria, Vicente E.; Cheng, Qingsha S.; Yu, Ming; Hoefer, Wolfgang J. R.; Rayas-Sánchez, José E.In this paper we honor Professor John W. Bandler and his legacy in RF and microwave modeling and automated design optimization. We showcase his pioneering breakthroughs in minimax optimization, p-th norm formulations, yield optimization, and nonlinear circuit design optimization. We highlight advances in direct EM microwave optimization, circuit response sensitivities, and efficient S-parameters sensitivity calculations. We explore the port-tuning version of space mapping for EM-based analysis, techniques for industrial microwave design of satellite systems, and post-manufacture hardware tuning. The integration of artificial neural networks with space mapping for enhanced EM-based design optimization and yield prediction, cognition-driven microwave filter design, and parallels between space mapping and artificial intelligence (AI) are examined. Finally, we speculate on the future integration of cognitive science with engineering design, leveraging the synergy of AI, machine learning, and space mapping.Ítem PCIe Gen6 physical layer equalization tuning by using unsupervised and supervised machine learning techniques(IEEE, 2023-12) Rangel-Patiño, Francisco; Viveros-Wacher, Andrés; Rayas-Sánchez, José E.; Vega-Ochoa, Édgar; Shival, Hemanth; Rodríguez-Saenz, SofíaÍtem Designing Platforms for Micro and Small Enterprises in Emerging Economies: Sharing Value through Open Innovation(MDPI, 2023-07) Osorno-Hinojosa, Roberto; Koria, Mikko; Ramírez-Vázquez, DeliaDelCarmen; Calvario, GabrielaÍtem One World, Two Ideas and Three Adaptations: Innovation Intermediaries Enabling Sustainable Open Innovation in University–Industry Collaboration in Finland, Mexico and Nicaragua(MDPI, 2022-09) Koria, Mikko; Osorno-Hinojosa, Roberto; Ramírez-Vázquez, DeliaDelCarmen; VanDenBroek, AntoniusÍtem Open innovation with value co-creation from university–industry collaboration(MDPI, 2022-01) Osorno-Hinojosa, Roberto; Koria, Mikko; Ramírez-Vázquez, DeliaDelCarmenÍtem A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization(IEEE, 2023-07) López-Araiza, Karla G.; Rangel-Patiño, Francisco E.; Ascencio-Blancarte, Jorge E.; Vega-Ochoa, Edgar A.; Rayas-Sánchez, José E.; Longoria-Gándara, Omar H.Ítem An overview on RF and microwave research in Latin America: scanning Latin American research on microwaves(IEEE, 2023-05-01) Rayas-Sánchez, José E.; Reynoso-Hernández, J. ApolinarÍtem Basic Space Mapping: A Retrospective and its Application to Design Optimization of Nonlinear RF and Microwave Circuits(IEEE, 2022-09) Rayas-Sánchez, José E.; Bandler, John W.Ítem An Early History of Optimization Technology for Automated Design of Microwave Circuits(IEEE, 2023-01) Rayas-Sánchez, José E.; Bandler, John W.Ítem System-Level Measurement-Based Design Optimization by Space Mapping Technology(IEEE, 2022-06-21) Rayas-Sánchez, José E.; Bandler, John W.Ítem EM‐driven tolerance optimization of compact microwave components using response feature surrogates(IEEE, 2022-06-21) Pietrenko‐Dabrowska, Anna; Slawomir, Koziel; Bandler, John W.; Rayas-Sánchez, José E.Ítem Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances(IEEE, 2022-03) Rayas-Sánchez, José E.; Moreno-Mojica, Aurea E.Ítem Fast jitter tolerance testing for high-speed serial links in post-silicon validation(IEEE, 2021-11) Viveros-Wacher, Andrés; Baca-Baylón, Ricardo; Silva-Cortés, Johana L.; Vega-Ochoa, Edgar A.; Rayas-Sánchez, José E.; Rangel-Patiño, Francisco E.Ítem Optimizing a buck voltage regulator and the number of decoupling capacitors for a PDN application(IEEE, 2021-05) Moreno-Mojica, Aurea E.; Rayas-Sánchez, José E.; Leal-Romo, Felipe J.Ítem Transmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4(IEEE, 2021-05) Ruiz-Urbina, Roberto J.; Rangel-Patiño, Francisco E.; Rayas-Sánchez, José E.; Vega-Ochoa, Édgar A.; Longoria-Gándara, Omar H.