A Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validation

Vista sencilla de ítem
dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorDuron-Rosales, Ismael
dc.contributor.authorHakim, Nagib
dc.date.accessioned2019-08-30T18:04:19Z
dc.date.available2019-08-30T18:04:19Z
dc.date.issued2016-12
dc.descriptionThe optimization of receiver analog circuitry in modern high-speed input/output (HSIO) links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose an innovative objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-Si validation time.es
dc.identifier.citationF.E. Rangel-Patino, A. Viveros-Wacher, J.E. Rayas-Sánchez, E.A. Vega-Ochoa, I. Duron-Rosales, and N. Hakim, “A holistic methodology for system margining and jitter tolerance optimization in post-silicon validation,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2016), Puerto Vallarta, Mexico, Dec. 2016, pp. 1-4. DOI: 10.1109/LAMC.2016.7851268es
dc.identifier.isbn978-1-5090-4288-3
dc.identifier.urihttp://hdl.handle.net/11117/6003
dc.language.isoenges
dc.publisherIEEEes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectPost-silicon Validationes
dc.subjectJitteres
dc.subjectSystem Margininges
dc.subjectEye Diagrames
dc.titleA Holistic Methodology for System Margining and Jitter Tolerance Optimization in Post-Silicon Validationes
dc.typeinfo:eu-repo/semantics/articlees
rei.peerreviewedYeses

Archivos

Bloque original
Mostrando 1 - 1 de 1
Miniatura
Nombre:
Rangel_16Dec_Holistic_SystMarg_Jitter_Opt_Author_ver.pdf
Tamaño:
755.78 KB
Formato:
Adobe Portable Document Format
Descargar

Colecciones

DESI - Artículos y ponencias con arbitraje