Serializer Design for a SerDes chip in 130nm CMOS Technology
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Fecha
2016-08
Autores
Arrambide-Barrón, Efraín
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ITESO
Resumen
Descripción
This document presents the digital Serializer module description and development, which will be part of a SerDes system in 130nm CMOS technology for PCI Express protocol communication applications. The code of Serializer was written in Verilog description language, and the logical and physical synthesis were performed using the following tools, Cadence Encounter Digital Implementation System (EDI) and Encounter RTL compiler.
Palabras clave
SerDes, PCI Express, Serializer Architecture, Verilog
Citación
Arrambide-Barrón, E. (2016). Serializer Design for a SerDes chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.