Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology

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dc.contributor.advisorMartínez-Guerrero, Esteban
dc.contributor.authorHernández-Flores, Jaime G.
dc.date.accessioned2020-11-05T21:26:11Z
dc.date.available2020-11-05T21:26:11Z
dc.date.issued2020-08
dc.descriptionThis document presents the design of a time amplifier circuit in 0.18 m CMOS process with a supply voltage of 1.8 V. Simulation results performed with typical process parameters, nominal supply voltage, room temperature and an operating frequency of 200 KHz, show a time gain of 200, with an error of less than 7%. The power consumption of the designed circuit is 26 W. The circuit can receive signals with a time difference from 10 ps to 4.7 nS. The layout dimension is 149.985 m x 168.536 m, with an area of 25.3 nm2.es_MX
dc.description.sponsorshipITESO, A. C.es
dc.identifier.citationHernández-Flores, J. G. (2020). Implementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.es_MX
dc.identifier.urihttps://hdl.handle.net/11117/6387
dc.language.isoenges_MX
dc.publisherITESOes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdfes_MX
dc.subjectTime Amplifieres_MX
dc.titleImplementing Time Amplifier for a Low Power SAR-ADC with Adaptive Conversion Cycle for High Quality Audio Applications in 0.18um TSMC CMOS Technologyes_MX
dc.typeinfo:eu-repo/semantics/academicSpecializationes_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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