Hardware Feasibility of Neural Network Branch Predictor

Abstract

AI has taken the engineering and computer science industry by storm due to its adaptability and convenience. Its use is now an expectation, and the protagonist is the transformer, as it is used in LLMs. However, the simple perceptron still has a role to play, and not all problems need a massive neural network. With this in mind, the purpose of this project is to simulate and implement a branch predictor using perceptron-based neural networks in System Verilog for a RISC-V processor design. The goal of this project is not necessarily to prove that a neural network is better than traditional branch predictor algorithms like TAGE, but to identify its uses and strengths relative to them, if any exist. In simple terms, a branch predictor’s job, as its name implies, is to predict the result of a conditional branch in the executed code. It has the necessary elements to exploit the perceptron’s ability to adjust its weights to reduce error by tracking correct and incorrect predictions. Two implementations were made: a Multi-Layer Perceptron and a Single-Layer Perceptron neural network, where the SLP surpasses the Bimodal and 2-bit branch predictors used for comparison, with results of SLP 98.72% / 98.22% vs Bimodal 97.72% / 95.13%. The caveat is less maximum frequency, as SLP has ∼30% more ALMs. This work combines two areas of engineering: neural networks, which are state-of-the-art in computer science, and branch predictors, which are a fundamental part of computer architecture. It could serve as a didactic tool to teach students how a branch predictor works, with a fairly competent implementation, or as an embedded system that needs a small branch predictor.