DESI - Trabajos de fin de Maestría en Diseño Electrónico
URI permanente para esta colecciónhttps://hdl.handle.net/11117/3264
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Ítem Acceso Abierto Implementation and Evaluation of Branch Predictors on RISC-V(ITESO, 2025-08) Martínez-Aceves, Braulio I.; Haro-Ruiz, LeonelThis work studies three branch prediction schemes for a pipelined RV32I core with a Reorder Buffer: an N-bit counter, a Global History Register (GHR) indexed counter array, and Gshare. The design integrates a Branch Target Buffer split into unconditional and conditional structures. Each predictor is modeled in C++ using the CBP 2016 framework to measure MPKI under an 8 KB storage budget. The algorithms are implemented in SystemVerilog, integrated into the RTL, and synthesized on an Intel MAX 10 FPGA. We also document a reproducible bare-metal build and load flow for C code: cross-compilation, linker script setup, memory image generation, and RTL loading. RTL simulation evaluates IPC and total cycles on Dhrystone, Qsort, and CoreMark workloads. C++ results show that Gshare reduces MPKI by 85.25% relative to a No BPU baseline with the same storage and outperforms GHR using the same counter and index settings. RTL results with a 15-bit index for simulation (7-bit index in synthesis due to resources) confirm the trend. Averaged across the three workloads, Gshare improves MPKI by 62.77%, IPC by 17.44%, and total cycles by 14.23% versus No BPU. Synthesis reports show modest hardware cost compared to baseline (about 38–40% more logic elements) and a small reduction in Fmax (about 8–10%). The results indicate that simple global-history predictors, and in particular Gshare, provide large accuracy and performance gains with minimal architectural complexity.Ítem Acceso Abierto Re-Decode: A General-Purpose CPU architecture model for extensive FU usage(ITESO, 2025-09) Padilla-Gutiérrez, Jorge A.; Vázquez-Tello, Carlos H.In the nature of current CPU architectures, the full utilization of the Functional Units (FUs) is not always accomplished, generating a negative impact on Instructions per Cycle (IPC). In order to get the best performance out of the FUs, the Re-Decode algorithm is implemented as an architectural model in the Gem5 architectural simulator; this model redirects the instructions in queue into similar instructions, mainly scalar or vector instructions, that will take advantage of unused FUs slots without changing the final result of the program. This architectural model takes advantage of the instructions affinity, defined as the capability of some instructions to obtain the same result value; the instructions with high affinity are pairs of General-Purpose operations and their respective Scalar operation for vector registers, as well as the Scalar operations with their respective Vector operations, meaning that regardless of being a General-Purpose Register (GPR) or a vector register with a Scalar value, the result of their execution will always be the same for an independent set of input values. This aims to distribute the instructions more efficiently between every FU, concluding with a higher IPC. The Re-Decode architectural model was able to increase up to 9% the IPC on a threaded workflow and reduce the number of instructions waiting for an FU by a factor of 52 times by being Re-Decoded.Ítem Acceso Abierto USB Through Network Performance and Cost Analysis of Solution in Data Center Applications(ITESO, 2025-05) Villagrán-López, María F.; Chávez-Hurtado, José L.This case study investigates the viability of USB-over-Ethernet (UTN) solutions in data center environments, focusing on performance, scalability, security, and cost. Through benchmarking tools like ATTO and DiskSPD, the study compares direct USB connections with UTN devices such as the SEH UTN Server Pro. Results show that while direct motherboard connections offer the best performance, UTN solutions outperform front panel USB ports and provide significant advantages in manageability and cost-efficiency. The SEH UTN Server Pro is highlighted for its superior encryption, access control, and centralized management features. The research concludes that UTN is a practical alternative for remote USB access in data centers, with room for improvement in network stability and small-block IOPS performance.Ítem Acceso Abierto Metodología para el diseño de filtros EMI(ITESO, 2025-08) Lozano-Torres, Juan C. O.; Tapia-Hernández, AlejandroActualmente, uno de los principales retos en el diseño de productos electrónicos, ya sea como productos de consumo, automotriz, médico, aeronáutico, incluso espacial, es alcanzar el desempeño para el cual fueron diseñados funcionalmente desde su definición y al mismo tiempo cumplir con las especificaciones requeridas y especificaciones del mercado para su futura comercialización. Estos requerimientos garantizan en gran parte la seguridad del usuario y la integración de estos productos con su entorno funcional. Principalmente uno de los retos a los cuales se enfrentan los ingenieros en electrónica en la actualidad es minimizar el fenómeno de emisiones radiadas y conducidas que existe entre los diversos dispositivos electrónicos que se encuentran operando dentro de un mismo entorno, mismo que, en caso de no comportarse dentro de los niveles indicados en los estándares y regulaciones pueden ocasionar el mal funcionamiento del producto e incluso, ocasionar problemas en otros dispositivos que se encuentren en su entorno. En este trabajo de investigación se busca desarrollar una metodología que permita analizar y optimizar el diseño de filtros EMI desde las primeras propuestas de diseño con el propósito de cumplir con los estándares de compatibilidad electromagnética. A través esta metodología se emplearán técnicas de análisis matemático y simulaciones de circuitos electrónicos que permitan evaluar condiciones de prueba teóricas y propuestas de mejora en los diseños y de esta manera predecir el comportamiento del producto en condiciones reales. En Continental Automotive los ingenieros en electrónica no cuentan con alguna metodología clara y única que permita diseñar y optimizar de manera anticipada los filtros EMI utilizados principalmente en fuentes conmutadas que se utilizan en los productos. Normalmente los circuitos utilizados en cada diseño son módulos generales de fuentes conmutadas y/o módulos analógico-digitales que procesan datos a alta velocidad, Dichos módulos típicamente cuentan con una propuesta inicial de diseño de filtro EMI dictada por el fabricante, en consecuencia, las optimizaciones se detectan después de realizar las primeras validaciones eléctricas, generando esta condición un incremento en costo y en el tiempo de validación. Este trabajo de investigación se enfocado al desarrollo de una metodología que permita desarrollar, analizar y optimizar el análisis de filtros EMI mediante el uso de simulaciones en el software ADS (Advanced Design System). El objetivo particular busca desarrollar una metodología que permita analizar el comportamiento y optimizar el diseño de filtros EMI durante etapas tempranas de diseño.Ítem Acceso Abierto Analysis of Indoor Localization Methods with Bluetooth Low Energy(ITESO, 2025-06) Zamora-Dávalos, Ricardo; Pardiñas-Mir, Jorge A.This case study presents a technical analysis of indoor distance estimation using Bluetooth Low Energy (BLE), with a particular focus on its integration into embedded systems. The study evaluates four key methodologies—Received Signal Strength Indication (RSSI), Time of Flight (ToF), Angle of Arrival (AoA), and Channel Sounding (CS)—highlighting their theoretical underpinnings, implementation characteristics, and practical performance. A primary contribution of this work lies in its comparative framework, which helps identify the most suitable BLE-based method depending on system requirements such as accuracy, power consumption, and hardware complexity. The study includes experimental implementations of RSSI and ToF using NXP’s MCX W71x platform, allowing for practical observations of BLE behavior under real-world conditions. Limitations in hardware accessibility restricted direct experimentation with AoA and CS; however, their inclusion is supported through publicly available demonstrations and validated references. These insights enable a balanced discussion between theoretical potential and real-world feasibility. The main contribution of this work is the structured comparison and contextual application of BLE-based distance estimation techniques. This allows system designers to make informed decisions aligned with application constraints and performance goals. The study also serves as a technical guide for those developing BLE localization systems in domains such as smart buildings, asset tracking, and IoT deployments. Overall, this work bridges the gap between theoretical methodologies and practical implementation, providing a foundation for future enhancements and hybrid approaches in BLE-based indoor localization systems.Ítem Acceso Abierto Implementation of a Hash Security Algorithm using an ARM Cortex M3 Soft Core(ITESO, 2025-07) Castro-González, Omar E.; Aguilera-Galicia, Cuauhtémoc R.This work presents the implementation of the SHA-3-512 hash algorithm on an ARM Cortex-M3 soft core deployed on an Xilinx Artix-7 FPGA. Initially, we introduce hash algorithms, outlining their role in ensuring data integrity, authentication, and security in various applications, including cryptography, digital signatures, and blockchain technology. We then delve into the inner workings of SHA-3-512, a member of the Keccak family, emphasizing its sponge construction and robust resistance to collision attacks, making it one of the most secure hash algorithms. The study details the acquisition of the ARM Cortex-M3 softcore from ARM’s DesignStart program, including modifications to streamline the softcore by removing unneeded peripherals and optimizing it for our specific application. Two implementations are developed: a pure software implementation, executed entirely on the ARM Cortex-M3, and a mixed hardware-software co-processor design that leverages the FPGA’s parallel processing capabilities to enhance performance. We compare the performance and resource utilization of both implementations, analyzing metrics such as execution time, power consumption, and FPGA resource usage. The results demonstrate that the mixed hardware-software co-processor achieves a performance improvement of 161 times that of the pure software implementation while maintaining efficient resource utilization. This case study highlights the advantages of hardware acceleration in cryptographic applications and provides insights into optimizing hash algorithm implementations on resource- constrained embedded systems.Ítem Acceso Abierto Metodología para acelerar la verificación pre-silicio con enfoque a firmware (FW)(ITESO, 2025-06) Linares-Altamirano, Martín R.; Avendano-Fernández, VíctorLas actuales tendencias en desarrollo de System on Chip(SoC) y sistemas multi-dado, han traído un nivel de complejidad nunca visto, generando grandes desafíos para el diseño y la verificación en etapas de pre-silicio. Dichos desafíos han sido incorporar en las pruebas del ambiente de verificación pre-silicio, flujos de software(SW) y/o firmware(FW) que normalmente corren en etapas de emulación y/o prototipado. Esto complica el desarrollo y ejecución de los ambientes de verificación, aumentando los tiempos de simulación y aumentando las dependencias y el manejo de estas. Parte de la problemática se deriva a que todo el diseño esta siendo simulado, desde el sistema de cómputo, los diferentes buses, memorias, periféricos e incluso las interfaces y puertos de debug, sin contar las adecuaciones que se tengan que hacer para cargar el programa en la simulación de pre-silicio. Una forma de reducir este problema es hacer uso de los modelos funcionales de los diseños, escritos en SystemC que permiten replicar el funcionamiento a alto nivel de los SoCs, desde la validación de una arquitectura, hasta ejecutar SW y sistemas operativos. Implementar una interfaz entre el modelo funcional en SystemC y el diseño en el ambiente de verificación permite la ejecución de pruebas con contenido de SW estimulando directamente el RTL al que está enfocada la misma. Reduciendo complejidades del ambiente, dependencias y facilitando opciones de debug.Ítem Acceso Abierto Design and Optimization of a Multi-Stage Receiver for a PCI Express Gen6.0 Link(ITESO, 2025-06) López-Araiza, Karla G.; Rangel-Patiño, Francisco E.The escalating demand for greater bandwidth, driven by the emergence of new applications has led to the development of the latest Peripheral Component Interconnect Express (PCIe) known as Gen6. This advancement achieves data rates of 64 giga-transfers per second (GT/s) and adopts the Pulse Amplitude Modulation 4-level (PAM4) signaling scheme. While PAM4 effectively addresses the need for increased bandwidth, it introduces new challenges in the design of the physical channel. Specifically, PAM4 is more susceptible to errors arising from various noise sources attributed to reduced voltage and timing ranges, resulting in a higher Bit Error Rate (BER). This phenomenon also brings additional complexities in areas such as slicers, transition jitter, and equalizers [1]; the inherent 1/3 eye amplitudes of PAM4 also result in a signal-to-noise ratio (SNR) penalty and transitions between non-adjacent levels diminish the width of the eye openings. Additionally, many undesired channel effects worsen with higher data rates making of equalization (EQ) a critical process for PAM4 signaling. In this thesis, a multi-stage continuous-time linear equalizer (CTLE) design with high-band, mid-band, and low-band frequency boost stages and a low frequency equalizer (LFEQ) is proposed to meet the requirements of a wide frequency range and channel losses. Due to the intricate nature of equalization for multi-level signals, optimization methods are employed including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning. Equalization settings are optimized to maximize the eye diagram for best link performance. The design verification as well as the optimization method proposal are evaluated through MATLAB SerDes Toolbox. The research conducted in this thesis resulted in a paper that was published in the IEEE Latin American Electron Devices Conference. The objective of this thesis is to provide a more detailed explanation of the findings presented in the previously published paper titled “A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization”.Ítem Acceso Abierto Diseño e implementación del curso de Fundamentos de microprocesadores y microcontroladores(ITESO, 2025-02) Sinsel-Duarte, Martín A.; Longoria-Gándara, Omar H.Esta tesis presenta el proceso de diseño e implementación del curso de Fundamentos de Microprocesadores y Microcontroladores que ofrece el Instituto Tecnológico y de Estudios Superiores de Occidente a partir de agosto de 2023. Este curso atiende a los procesos de mejora continua que requiere el Consejo de Acreditación de Enseñanza de la Ingeniería (CACEI), y se ofrece como curso obligatorio para las carreras de Ingeniería en Electrónica, Ingeniería en Sistemas Digitales Embebidos e Ingeniería en Mecatrónica. El proceso implicó una revisión del uso de los microcontroladores en la academia, a nivel licenciatura, y su vínculo con la industria. Así mismo se analizaron algunas de las estrategias didácticas utilizadas para enseñar estas tecnologías a nivel universitario. A lo largo del documento, se desglosa la propuesta del curso en los elementos constitutivos de la guía de aprendizaje, y se presentan los materiales didácticos elaborados, programas de ejemplo y las actividades de aprendizaje, orientados a lograr los objetivos del curso.Ítem Acceso Abierto Optimization of a TSPC D flip-flop using MatLab(ITESO, 2025-01) Martínez-Flores, Iván; Chávez-Hurtado, José L.The central focus of this case study is the simulation and optimization of a True Single Phase Clock (TSPC) D flip-flop using WinSpice for circuit simulation and MATLAB for optimization. The primary objective of this TOG is to minimize the setup time of the TSPC D flip-flop, thereby enabling faster input processing and improving overall circuit performance. This was achieved using the embedded codes in MATLAB, which included fminsearch, fmincon, and genetic algorithms. These algorithms were used to find the optimal transistor dimensions without requiring a manual implementation. A TSPC D flip-flop is a specialized version of a D flip-flop that operates with a single-phase clock throughout its design. It avoids using a negated clock signal that can introduce unwanted delays and timing issues. This characteristic makes it particularly suited for high-speed applications. Appendix A contains the complete codebase, including the scripts used for each function and their corresponding file names. This appendix ensures the reproducibility of the results and provides a detailed reference for future researchers seeking to replicate or extend this study.Ítem Acceso Abierto A Practical Start with Zephyr RTOS(ITESO, 2024-12) Ramírez-Sánchez, Earl O.; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.The field of embedded systems has grown significantly in recent years, driving increased demand for advanced Real-Time Operating Systems (RTOS). These systems manage complex tasks, ensure fast responses, and optimize resource usage. Zephyr RTOS stands out as an open-source solution with solid community support and compatibility across various hardware platforms. Supported by the Linux Foundation, its modular design makes it an appealing choice for scalable and customizable solutions. However, new users often face challenges when configuring it for hardware that lacks native support, especially when working with Devicetree structures and Kconfig files. While powerful, these components require a solid understanding of system configuration and hardware integration. This case study provides a practical guide to reduce the learning curve and help developers adapt Zephyr to their projects. It covers critical topics such as adding hardware support for the NXP FRDM-K66F board and a Liquid Crystal Display (LCD) with the PCD8544 controller, handling interrupts, managing multithreading and synchronization, and integrating external devices.Ítem Acceso Abierto Machine Learning Algorithms for Small Datasets with Reinforcement Learning and Optimization(ITESO, 2024-10) Soule-Ascencio, Santiago; Gómez-Cortés, ArturoAs computers evolve and their computational complexity and performance increase, many forms of machine learning have found new implementations and applications to take advantage of these computer features. Previously, areas dominated exclusively by purpose-built software or fully manual applications have found newly developed innovation from Machine Learning development. Reinforcement Learning is a way to implement some algorithms that are being explored. Working in a similar way to teaching a young child to perform a task by giving positive or negative feedback depending on their actions, this form of machine learning has great potential with some disadvantages. The results can sometimes greatly outperform computational deterministic implementations. Being an unexplored area, this investigation has the purpose of implementing and comparing multiple machine learning algorithms with a reinforcement learning optimization algorithm to find out the advantages and disadvantages of each one. Most of the research involves a reinforcement learning Intel project that would benefit greatly from the results of this investigation and will also suggest that there are certain restrictions that the algorithm implementations must follow. It is also the goal of the investigation to find which algorithm is the most optimal for the Intel project mentioned. Benchmarking and thorough testing will be done with a real system and implementation of each algorithm to compare objective data during the investigation, as well as an analysis of advantages and harmful properties of each algorithm. Results will be published in the last sections of the document with as much detail as possible without giving confidential information from Intel’s intellectual property.Ítem Acceso Abierto Availability under threat - CXL Type 3 Vulnerability Assessment(ITESO, 2024-07) Vite-López, Erick E.; Gradilla-Negrete, Ramón E.The growing demand for data processing, driven by technologies such as artificial intelligence, has led the industry to seek more efficient solutions. The Compute Express Link (CXL) protocol stands out as a promising option, offering high-speed, low-latency interconnections between the CPU and other devices, thereby improving resource management, and facilitating the scaling of data-intensive applications. A case study of how the availability of a system could be compromised through a DoS attack targeting the CXL protocol is presented. The context of this work is based on a controlled, secure, and dedicated environment for this research. At no point is a real system/server compromised, and the study is based on the Next Generation Intel® Xeon Server CPU and a CXL type 3 test card. Established in 2019 and publishing the first official specification of the CXL protocol, called CXL 1.0, in March 2020, The CXL Consortium is an open industry standards group established to create technical specifications that enable groundbreaking performance for new usage models, while also supporting an open ecosystem for data center accelerators and other high-speed enhancements. Considering that the protocol is relatively young compared to other protocols, such as PCIe (Peripheral Component Interconnect Express), the "threat modeling" methodology will be followed to identify vulnerabilities that could potentially compromise the system's availability.Ítem Acceso Abierto Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology(ITESO, 2024-11) Jiménez-González, Mario A.; Martínez-Guerrero, Esteban; Aguilera-Galicia, Cuauhtémoc R.This thesis presents a 12-bit ΣΔ ADC design on 45 nm CMOS technology for MEMS sensor applications. The design was performed using Virtuoso Cadence tools. The circuit is composed by a first-order ΣΔ Modulator, a CIC filter, and a Decimator. The first-order ΣΔ Modulator having an oversampling ratio K=128 is developed implementing the switched-capacitor technique. The first-order ΣΔ Modulator is composed by an integrator, a comparator, and a 1-bit DAC. Simulation results show how the Modulator changes the output transitions frequency depending on the input voltage value, being K=128 the best tradeoff between the number of modulations and circuit complexity. The physical design of this block is fully customized. For the digital filter and decimator blocks, a third-order Cascaded Integrator Comb (CIC) filter is developed as a Verilog macro model to test and measure the transient and spectral response of the ADC, as well as its main Figures of Merit.Ítem Acceso Abierto Plataforma óptica experimental Tosa Rosa(ITESO, 2024-09) Castro-Alba, Raymundo; Pardiñas-Mir, Jorge A.Este trabajo de obtención de grado presenta el marco que he desarrollado para la formación de ingenieros de análisis de fallas y personal técnico en el tema de las comunicaciones ópticas, con el objetivo de apoyar el análisis del funcionamiento y las fallas presentes en dispositivos de transmisión y recepción óptica, área de trabajo de la empresa en donde laboro. El trabajo está dividido en dos: la descripción de los principios de las comunicaciones ópticas y el desarrollo y uso de una plataforma experimental. La primera parte describe los elementos más relevantes para el contexto del trabajo de análisis de funcionamiento y fallas en módems ópticos: Redes y Módems Ópticos, Fundamentos de Óptica, Láser y Fotodetectores PIN-APD, Fibras Ópticas, Transmisores Ópticos y Receptores Ópticos. La segunda parte describe la plataforma experimental, la cual es un sistema mínimo de comunicaciones ópticas que contiene un transmisor TOSA (Transmitter Optical SubAssembly), un receptor ROSA (Receiver Optical SubAssembly), y la fibra óptica como medio de transmisión. Con la plataforma óptica se pueden entender varios elementos de un módem óptico como son: El láser, los diodos PIN, la fibra óptica y el acondicionamiento de señal. La capacitación, objetivo de las evidencias presentadas en este trabajo, ha sido impartida a técnicos e ingenieros y se han obtenido buenos resultados en relación con la reducción de un bonepile (conjunto de tarjetas electrónicas con fallas funcionales) de 15 millones a 2 millones de dólares.Ítem Acceso Abierto RISC-V Floating Point Unit(ITESO, 2024-09) Alfaro-Gómez, Ricardo A.; Alvarado-Lagunes, Julián; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.This document explores the representation and processing of arithmetic data, with a focus on Floating Point (FP) operations for RISC-V architecture. It introduces the IEEE 754 standard for FP representation, detailing its evolution and significance in achieving portability and reliability in hardware units. Challenges associated with FP operations, such as high storage and execution costs, are addressed, necessitating dedicated Floating Point Units (FPUs) to optimize performance. The document proposes the implementation of an FPU for RISC-V architecture as a means to align with industry standards and contribute to scientific advancements. It discusses various number representations, the IEEE FP standard, and the role of FPUs within processor designs. Additionally, it outlines the problem statement, objectives, and expected impact of FPU implementation, providing insights into the division and square root algorithms used for FPU implementation. Overall, this document provides a comprehensive overview of FP operations, the IEEE 754 standard, FPU implementation challenges, and the significance of RISC-V architecture in contemporary computing.Ítem Acceso Abierto Compute Express Link Optimization for Low Latency(ITESO, 2024-05) Baltazar-Ortiz, Ángel A.; Rangel-Patiño, Franciso E.This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.Ítem Acceso Abierto Smart Audio Equalizer(ITESO, 2024-02) Teyssier-Ramírez, Luis A.; Longoria-Gándara, Omar H.En la actualidad, las personas suelen escuchar música en diferentes dispositivos, tales como teléfonos inteligentes, altavoces portátiles o sistemas de infotenimiento en automóviles. Sin embargo, algunas desconocen que estos dispositivos ya vienen equipados con ecualizadores de audio integrados, mientras que otros no saben cómo ajustarlos para obtener la mejor calidad de audio y mejorar la experiencia auditiva. En este proyecto de tesis, se propone una forma inteligente de ecualización de audio mediante inteligencia artificial. Se aplican automáticamente configuraciones preestablecidas de ecualización según el género musical que es determinado por un algoritmo. Se analizaron y compararon dos tipos de ecualizadores. Luego, se creó una aplicación en Matlab como prueba de concepto para demostrar las ventajas de estos ecualizadores y para implementar un proceso de etiquetado automático que utiliza técnicas de Recuperación de Información Musical (MIR) y un modelo de Red Neuronal Convolucional (CNN) incluido en la biblioteca Essentia. Los resultados del etiquetado se analizaron y discutieron para evaluar el rendimiento del modelo de aprendizaje profundo de Essentia, que se incorporó en la aplicación. En el futuro, este modelo podría entrenarse con diferentes conjuntos de datos que incluyan más géneros musicales, lo que mejoraría su funcionalidad. Además, podría implementarse en un dispositivo integrado utilizando soluciones de código abierto como Android Auto, para emular un sistema integrado como el de un sistema de infotenimiento en un automóvil.Ítem Embargo Application-Specific Integrated Circuit of an Inter-IC Sound Digital Filter for Audio Systems(ITESO, 2024-02) Dávila-Velarde, René S.; Longoria-Gándara, Omar H.Ítem Acceso Abierto Transitioning to a High-Performance Team that Possesses Advanced Technical Skills(ITESO, 2023-10) Pérez-Hernández, Paul; Longoria-Gándara, Omar H.