DESI - Trabajos de fin de Maestría en Diseño Electrónico
URI permanente para esta colecciónhttps://hdl.handle.net/11117/3264
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Ítem Acceso Abierto Sistema Integrado de Navegación con IMU y GPS para Vehículos Autónomos Basado en el Filtro de Kalman(ITESO, 2026-06) Abrica-Lara, Alexander; González-Jiménez, Luis E.; García-Huerta, Raúl A.El uso de vehículos aéreos no tripulados ha aumentado en las últimas décadas debido a los diversos servicios que ofrecen. Pero la mayoría de las personas utiliza estas aeronaves sin conocer las ciencias aplicadas necesarias para desarrollar un modelo propio. El objetivo es implementar un prototipo de bajo costo que permita a cualquier persona, sin importar que no tenga conocimientos ni experiencia previa con drones, adquirir las bases necesarias para desempeñarse en aplicaciones de vehículos aéreos no tripulados. El documento expone las teorías fundamentales sobre las transformaciones de cuerpos rígidos, su traslación y rotación, facilitando así la comprensión matemática y la interpretación en modelos lineales para estimar valores y contrastarlos con mediciones ruidosas. Asimismo, se presentan ejemplos de sensores y módulos básicos para su implementación, el procesamiento de datos y su reinterpretación para su integración en el diseño del vehículo autónomo. Antes de abordar el diseño, se guía al lector en la obtención de los valores de covarianza de cada sensor y módulo, con el fin de comprender cómo reducir los errores de medición y de proceso en el sistema lineal. Una vez identificadas todas las variables, se procede al diseño e implementación de los sistemas de observación de estado que permiten estimar la orientación y la posición del vehículo. Finalmente, se analizan los resultados obtenidos en distintos experimentos que pondrán a prueba si las estimaciones de orientación y posición se aproximan a la verdad fundamental propuesta.Ítem Acceso Abierto Upgrade to Intelligent Module UPU: Power Stage(ITESO, 2025-12) González-Ávalos, Diego A.; DelRey-Acuña, Juan R.The present work shows the design upgrade of an intelligent control module used in home automation systems to manage home devices such a lamps, actuators or motors. The design upgrade and information used in this document have been developed for exclusively academic and educational purposes. The module is part of set of multifunction modules and software tools of the LCN® system (Local Control Network) from the company Issendorff KG. The described module which is called LCN-UPU is a sensor/actuator module which has two switching/dimming electronic outputs for 120VAC. The outputs can be operated as leading and trailing edge dimmer or in switching operation as zero voltage switch.[1] The design upgrade of the LCN-UPU was based on a partial reverse engineering process, the understanding of the module requirements and the detected needs on the local market (Mexico region). For a better understanding of the LCN-UPU module the upgrade was addressed in two sections: Digital and Power stage, in this work the Power stage is covered. Main upgrade on Power stage is the increase from two to three switching/dimming electronic outputs, additionally two high current outputs are now included to extend the module capabilities. The design procedure to increase the PCB space availability (required to increase the power outputs) started on the downsizing process of the output transistors and it is described in Chapter 1. Then, a short mention about the relay used to drive the high-power outputs is presented in Chapter 2. A comparison between the previous and the new design is presented in Chapter 3 emphasizing the trade-off between the cost and technical benefits. Finally, new design (schematic & PCB layout) are presented in Chapter 4.Ítem Acceso Abierto High-Speed USB4 Interface: Validation across Gen 2 and Gen 3 Variants(ITESO, 2025-09) Osobampo-Mendoza, Cassandra Y.; Silva-Martínez, Miguel; Ruiz-Urbina, Roberto J.The increasing demand for higher data rates is driving the development of new USB generations, which introduce new challenges in post-silicon validation. The complexity of new compliance tests, instruments, and electrical parameters in USB products demands extensive knowledge and understanding of signal integrity requirements for high-speed protocols. This is because high-frequency data rates are more susceptible to degradation caused by factors such as attenuation, crosstalk, EMI, and reflections. In this master’s dissertation, we present a methodology guide for USB4 Tx and Rx testing, to expedite the process for engineers to fully understand the electrical and compliance test specifications of USB4. This document aims to help engineers quickly familiarize themselves with each parameter, required tests, recommended cables, fixtures, and instruments, enabling them to commence validation promptly.Ítem Acceso Abierto A Practical Start with Zephyr RTOS(ITESO, 2024-12) Ramírez-Sánchez, Earl O.; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.The field of embedded systems has grown significantly in recent years, driving increased demand for advanced Real-Time Operating Systems (RTOS). These systems manage complex tasks, ensure fast responses, and optimize resource usage. Zephyr RTOS stands out as an open-source solution with solid community support and compatibility across various hardware platforms. Supported by the Linux Foundation, its modular design makes it an appealing choice for scalable and customizable solutions. However, new users often face challenges when configuring it for hardware that lacks native support, especially when working with Devicetree structures and Kconfig files. While powerful, these components require a solid understanding of system configuration and hardware integration. This case study provides a practical guide to reduce the learning curve and help developers adapt Zephyr to their projects. It covers critical topics such as adding hardware support for the NXP FRDM-K66F board and a Liquid Crystal Display (LCD) with the PCD8544 controller, handling interrupts, managing multithreading and synchronization, and integrating external devices.Ítem Acceso Abierto Machine Learning Algorithms for Small Datasets with Reinforcement Learning and Optimization(ITESO, 2024-10) Soule-Ascencio, Santiago; Gómez-Cortés, ArturoAs computers evolve and their computational complexity and performance increase, many forms of machine learning have found new implementations and applications to take advantage of these computer features. Previously, areas dominated exclusively by purpose-built software or fully manual applications have found newly developed innovation from Machine Learning development. Reinforcement Learning is a way to implement some algorithms that are being explored. Working in a similar way to teaching a young child to perform a task by giving positive or negative feedback depending on their actions, this form of machine learning has great potential with some disadvantages. The results can sometimes greatly outperform computational deterministic implementations. Being an unexplored area, this investigation has the purpose of implementing and comparing multiple machine learning algorithms with a reinforcement learning optimization algorithm to find out the advantages and disadvantages of each one. Most of the research involves a reinforcement learning Intel project that would benefit greatly from the results of this investigation and will also suggest that there are certain restrictions that the algorithm implementations must follow. It is also the goal of the investigation to find which algorithm is the most optimal for the Intel project mentioned. Benchmarking and thorough testing will be done with a real system and implementation of each algorithm to compare objective data during the investigation, as well as an analysis of advantages and harmful properties of each algorithm. Results will be published in the last sections of the document with as much detail as possible without giving confidential information from Intel’s intellectual property.Ítem Acceso Abierto Compute Express Link Optimization for Low Latency(ITESO, 2024-05) Baltazar-Ortiz, Ángel A.; Rangel-Patiño, Francisco E.This thesis delves into the architecture of the Compute Express Link® (CXL®) 1.1 specification, which is built on top of the physical and electrical interface of the peripheral component interconnect express® (PCIe®) Gen 5. CXL is a technology focused on efficiently handling generative artificial intelligence (AI) and its enormous memory performance demands. CXL enables coherency between the central processing unit (CPU) memory space and memory connected under devices for memory pooling. As CXL technology gains traction, optimizing latency has become a significant area for improvement. Fortunately, new configurations are available that can improve the user experience for advanced workloads. One way to reduce latency is to use the equalization process in fixed mode during CXL link bring-up and avoid recoveries or retries under the link training state machine (LTSSM) setup that are continuously triggered due to the bit error. Some equalizers are subject to operate in dynamic mode and require real-time latency optimization. The purpose of this thesis is to demonstrate the advantages and disadvantages of different optimization methods using latency measurement tools that are applicable only on the CXL validation stage. The study also utilizes optimization techniques implemented in MATLAB to determine the minimum global solution of an objective function. This research suggests that creating tools that can monitor, analyze, and control the optimal CXL link latency can contribute and improve significantly to future CXL technology implementations.Ítem Acceso Abierto Post-Silicon Functional Validation of a DDR5 Memory Controller(ITESO, 2023-10) Hernández-Reyes, Federico J.; Longoria-Gándara, Omar H.Ítem Acceso Abierto Plataforma de info-entretenimiento basado en Android Automotive PIE 9(ITESO, 2023-06) Gutiérrez-Tirado, José A.; López-Flores, Juan E.; Santos-Lechuga, Isidro; Huidobro-García, Víctor H.Ítem Acceso Abierto Formación técnica complementaria y proyectos de impacto. Diseño electrónico en alta frecuencia(ITESO, 2016-01) Moreyra-González, Rogelio A.; Rayas-Sánchez, José E.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en diseño de circuitos integrados(ITESO, 2021-08) Soto-Ramírez, Guillermo; Longoria-Gándara, Omar H.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en diseño electrónico de alta frecuencia(ITESO, 2021-08) Ramírez-Ruiz, José A.; Longoria-Gándara, Omar H.Ítem Acceso Abierto Estudio para mejorar la identificación de problemas de software(ITESO, 2021-05) Zamora-Cortés, Miguel J.; Rizo-Domínguez, LuisÍtem Acceso Abierto Reporte de formación complementaria en área de concentración en diseño electrónico de alta frecuencia(ITESO, 2021-03) Alfaro-Flores, Ivonne; Longoria-Gándara, Omar H.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en Diseño Electrónico de Alta Frecuencia(ITESO, 2020-09) Galindo-Vergara, Adriana E.; Longoria-Gándara, Omar H.Ítem Acceso Abierto Antenna Design Optimization Through Input Space Mapping(ITESO, 2020-05) Michel-Camacho, Eduardo; Brito-Brito, ZabdielÍtem Acceso Abierto Modelado de interferencias de propagación de señales de alta frecuencia en líneas de transmisión ideales(ITESO, 2020-01) López-Félix, Carlos C.; Brito-Brito, Zabdiel; Brito-Brito, ZabdielÍtem Acceso Abierto Diseño de filtro rechaza banda y cálculo de Antipad para un PCB de alta velocidad(ITESO, 2019-08) DeLaTorre-Aguirre, Jaime; Chávez-Hurtado, José L.; Chávez-Hurtado, José L.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en Alta Frecuencia(ITESO, 2019-04) Morales-Guerrero, Ernesto; Chávez-Hurtado, José L.; Chávez-Hurtado, José L.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en sistemas embebidos y telecomunicaciones(ITESO, 2018-05) Bernardo-Aldana, Juan E.; Chávez-Hurtado, José L.; Chávez-Hurtado, José L.Ítem Acceso Abierto Reporte de formación complementaria en área de concentración en diseño de circuitos integrados analógicos(ITESO, 2018-10) Gómez-Cruz, César T.; Chávez-Hurtado, José L.; Brito-Brito, Zabdiel; Brito-Brito, Zabdiel