Implementation of Vector Engine for RISCV Architecture

Abstract

The RISC-V Vector Extension introduces new capabilities for parallel data processing through vector operations that enhance performance in artificial intelligence (AI) and high-performance computing applications. In this thesis work, a Vector Engine is designed and implemented based on the RISC-V specification, supporting a core subset of arithmetic, logical, comparison, masking, and permutation operations. The implementation focuses on optimizing hardware resources while maintaining alignment with the RISC-V architectural model. A complete hardware design flow was carried out, including microarchitecture definition, Register-Transfer Level (RTL) modeling, functional verification using the Universal Verification Methodology (UVM), and physical synthesis across multiple semiconductor technologies. This work provides an efficient and scalable hardware solution that can serve as an alternative to GPUs for AI and data-parallel workloads in embedded and low-power systems.