Design and Optimization of a Multi-Stage Receiver for a PCI Express Gen6.0 Link

Abstract

The escalating demand for greater bandwidth, driven by the emergence of new applications has led to the development of the latest Peripheral Component Interconnect Express (PCIe) known as Gen6. This advancement achieves data rates of 64 giga-transfers per second (GT/s) and adopts the Pulse Amplitude Modulation 4-level (PAM4) signaling scheme. While PAM4 effectively addresses the need for increased bandwidth, it introduces new challenges in the design of the physical channel. Specifically, PAM4 is more susceptible to errors arising from various noise sources attributed to reduced voltage and timing ranges, resulting in a higher Bit Error Rate (BER). This phenomenon also brings additional complexities in areas such as slicers, transition jitter, and equalizers [1]; the inherent 1/3 eye amplitudes of PAM4 also result in a signal-to-noise ratio (SNR) penalty and transitions between non-adjacent levels diminish the width of the eye openings. Additionally, many undesired channel effects worsen with higher data rates making of equalization (EQ) a critical process for PAM4 signaling. In this thesis, a multi-stage continuous-time linear equalizer (CTLE) design with high-band, mid-band, and low-band frequency boost stages and a low frequency equalizer (LFEQ) is proposed to meet the requirements of a wide frequency range and channel losses. Due to the intricate nature of equalization for multi-level signals, optimization methods are employed including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning. Equalization settings are optimized to maximize the eye diagram for best link performance. The design verification as well as the optimization method proposal are evaluated through MATLAB SerDes Toolbox. The research conducted in this thesis resulted in a paper that was published in the IEEE Latin American Electron Devices Conference. The objective of this thesis is to provide a more detailed explanation of the findings presented in the previously published paper titled “A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization”.