Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect
| dc.contributor.author | Brito-Brito, Zabdiel | |
| dc.contributor.author | Rayas-Sánchez, José E. | |
| dc.contributor.author | DelRey, Juan R. | |
| dc.date.accessioned | 2017-05-11T16:25:00Z | |
| dc.date.issued | 2015-03 | |
| dc.description | This work analyzes a USB differential pair transmission line achieved in an inexpensive standard PCB laminate that is aimed for the Internet of Things ecosystem. An initial simulation in Sonnet EM simulator of the most basic structure is presented, along with a preliminary electromagnetics-based design as well as a basic EMC analysis under the IEC 61000-4-2 standard. In addition, the analysis of a known and well characterized differential structure is presented in order to set its response as a calibration reference. These initial simulations are intended to set the foundations for a more accurate model in a future work. | es |
| dc.description.sponsorship | ITESO, A.C. | es |
| dc.description.sponsorship | Freescale Semiconductor Mexico, S de RL | es |
| dc.identifier.citation | J. Rafael del-Rey, Z. Brito-Brito, and J. E. Rayas-Sánchez, “Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect,” in IEEE Latin-American Test Symp. (LATS-2015), Puerto Vallarta, Mexico, Mar. 2015, pp. 1-5. (INSPEC: 15111168, DOI: 10.1109/LATW.2015.7102514). | es |
| dc.identifier.other | DOI: 10.1109/LATW.2015.7102514 | |
| dc.identifier.other | INSPEC: 15111168 | |
| dc.identifier.uri | http://hdl.handle.net/11117/4487 | |
| dc.language.iso | eng | es |
| dc.publisher | IEEE Latin-American Test Symposium (LATS-2015) | es |
| dc.relation.ispartofseries | IEEE Latin-American Test Symposium (LATS-2015); | |
| dc.rights.uri | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdf | es |
| dc.subject | Impedance Matching | es |
| dc.subject | Coplanar | es |
| dc.subject | Waveguide Differential | es |
| dc.subject | IoT | es |
| dc.title | Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect | es |
| dc.type | info:eu-repo/semantics/conferencePaper | es |
| rei.embargo.lift | 10000-01-01 | |
| rei.embargo.terms | siempre | es |
| rei.peerreviewed | Yes | es |
| rei.revisor | IEEE Latin-American Test Symposium (LATS-2015) |