Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology

Vista sencilla de ítem
dc.contributor.authorConde-Almada, Ernesto
dc.contributor.directorMartínez-Guerrero, Esteban
dc.contributor.directorJuárez-Hernández, Esdras
dc.date.accessioned2016-09-06T18:28:01Z
dc.date.available2016-09-06T18:28:01Z
dc.date.issued2016-07
dc.descriptionAn analog receiver module for a SerDes with a data rate of 2.5 Gbps for PCI Express Gen 1, is presented. The module is composed by a high-speed differential amplifier, a replica bias circuit and a CML to CMOS converter with duty-cycle correction. The circuit was designed in CMOS 130nm process technology with a supply voltage of 1.2V. A high gain amplifier using the selfcascode technique allows to overcome the low output impedance limitation set by the 130nm technology. Simulation results show no functional issues under PVT corners and mismatch conditions, accomplishing PCI Express Gen 1 specifications.es
dc.description.sponsorshipConsejo Nacional de Ciencia y Tecnologíaes
dc.identifier.citationConde-Almada, E. (2016). Design and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.es
dc.identifier.urihttp://hdl.handle.net/11117/3848
dc.language.isoenges
dc.publisherITESOes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdfes
dc.subjectAnaloges
dc.subjectReceiveres
dc.subjectPCI Expresses
dc.subjectSerDeses
dc.subjectHigh-Speed Ies
dc.subjectO’ses
dc.subjectDuty Cycle Correctiones
dc.subjectCMLes
dc.subjectIC Designes
dc.titleDesign and Physical Implementation of an Analog Receiver for a SerDes System on Chip in 130nm CMOS Technologyes
dc.typeinfo:eu-repo/semantics/academicSpecializationes
rei.peerreviewedYeses

Archivos

Bloque original
Mostrando 1 - 1 de 1
Miniatura
Nombre:
Design and Physical Implementation of an Analog Receiver for a SerDes System On Chip in 130 nm CMOS Technology.pdf
Tamaño:
5.1 MB
Formato:
Adobe Portable Document Format
Descripción:
Descargar

Colecciones

DESI - Trabajos de fin de Especialidad en Diseño de Sistemas en Chip