A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation

Vista sencilla de ítem
dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorDuron-Rosales, Ismael
dc.contributor.authorVega-Ochoa, Édgar A.
dc.contributor.authorHakim, Nagib
dc.contributor.authorLópez-Miralrio, Enrique
dc.date.accessioned2020-06-12T21:29:40Z
dc.date.available2020-06-12T21:29:40Z
dc.date.issued2020-06
dc.descriptionThere is an increasingly higher number of mixed-signal circuits within microprocessors and systems on chip (SoC). A significant portion of them corresponds to high-speed input/output (HSIO) links. Post-silicon validation of HSIO links can be critical for making a product release qualification decision under aggressive launch schedules. The optimization of receiver analog circuitry in modern HSIO links is a very time consuming post-silicon validation process. Current industrial practices are based on exhaustive enumeration methods to improve either the system margins or the jitter tolerance compliance test. In this paper, these two requirements are addressed in a holistic optimization-based approach. We propose a novel objective function based on these two metrics. Our method employs Kriging to build a surrogate model based on system margining and jitter tolerance measurements. The proposed method, tested with three different realistic server HSIO links, is able to deliver optimal system margins and guarantee jitter tolerance compliance while substantially decreasing the typical post-silicon validation time.es_MX
dc.description.sponsorshipITESO, A.C.es_MX
dc.identifier.citationF.E. Rangel-Patiño, A. Viveros-Wacher, J.E. Rayas-Sánchez, I. Durón-Rosales, E.A. Vega-Ochoa, N. Hakim, and E. López-Miralrio, A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation, IEEE Trans. Emerging Topics Computing,8( 2): 453-463, Apr.-Jun. 2020. DOI: 10.1109/TETC.2017.2757937es_MX
dc.identifier.issn2376-4562
dc.identifier.urihttps://hdl.handle.net/11117/6236
dc.language.isoenges_MX
dc.publisherIEEEes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectBit-error-ratees_MX
dc.subjectDoEes_MX
dc.subjectEqualizationes_MX
dc.subjectEye-diagrames_MX
dc.subjectHigh-speed serial I/Oes_MX
dc.subjectInterconnectses_MX
dc.subjectJitteres_MX
dc.subjectKriginges_MX
dc.subjectOptimizationes_MX
dc.subjectPost-Si validationes_MX
dc.subjectReceiveres_MX
dc.subjectSerDeses_MX
dc.subjectTransmitteres_MX
dc.titleA Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validationes_MX
dc.typeinfo:eu-repo/semantics/articlees_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

Archivos

Bloque original
Mostrando 1 - 1 de 1
Miniatura
Nombre:
Rangel_17Sep_May_Holistic_SM_Jitter_PSV_AuthorVer.pdf
Tamaño:
2.06 MB
Formato:
Adobe Portable Document Format
Descripción:
Descargar

Colecciones

DESI - Artículos y ponencias con arbitraje