PCI Express Gen6 FIR Filter Optimization by Space Mapping for Post-Silicon Validation

Vista sencilla de ítem
dc.contributor.authorRangel-Patiño, Francisco
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorMoreno-Mojica, Aurea E.
dc.date.accessioned2025-04-09T21:23:33Z
dc.date.available2025-04-09T21:23:33Z
dc.date.issued2025-01
dc.description.abstractThe evolution of PCI Express technology to Gen6, and the forthcoming Gen7, has markedly increased data transfer speeds, presenting new challenges for signal integrity. To tackle these challenges, advanced design strategies, such as enhanced equalization (EQ) techniques, are necessary. Traditional EQ methods typically involve extensive laboratory measurements, rendering the EQ process highly time intensive. In this paper, we introduce an optimization methodology for the PCIe Gen6 transmitter (Tx) equalizer utilizing the Aggressive Space Mapping (ASM) algorithm. Our ASM approach employs a computationally efficient surrogate as coarse model to estimate eye diagram margins. An implicit mapping between the coarse and fine model equalizer settings is established, leading to an efficient optimization for the EQ tuning process. The effectiveness of the ASM methodology is confirmed through simulations with the MATLAB SerDes Toolbox, resulting in notable enhancements in the eye diagram area and overall system margins.
dc.description.sponsorshipITESO, A.C.es_MX
dc.identifier.citationF. E. Rangel-Patiño, J. E. Rayas-Sánchez, and A. E. Moreno-Mojica. PCI Express Gen6 FIR filter optimization by space mapping for post-silicon validation, in IEEE MTT-S Latin America Microwave Conf. (LAMC-2025), San Juan, Puerto Rico, Jan. 2025, pp. 104-107.
dc.identifier.isbn979-8-3315-4041-8
dc.identifier.urihttps://hdl.handle.net/11117/11497
dc.language.isoeng
dc.publisherIEEE
dc.relation.ispartofseriesIEEE MTT-S Latin America Microwave Conference (LAMC-2025)
dc.rights.urihttps://creativecommons.org/licenses/by-nc-nd/4.0/deed.es
dc.subjectAggressive Space Mapping
dc.subjectGaussian Process Regression
dc.subjectPCIe
dc.subjectPost-silicon Validation
dc.subjectSignal Integrity
dc.subjectTransmitter Equalizer
dc.titlePCI Express Gen6 FIR Filter Optimization by Space Mapping for Post-Silicon Validation
dc.typeinfo:eu-repo/semantics/article
dc.type.versioninfo:eu-repo/semantics/publishedVersion

Archivos

Bloque original
Mostrando 1 - 1 de 1
Miniatura
Nombre:
PCI Express Gen6 FIR Filter Optimization.pdf
Tamaño:
1003.55 KB
Formato:
Adobe Portable Document Format
Descargar

Colecciones

DESI - Artículos y ponencias con arbitraje