Transmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4

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dc.contributor.authorRuiz-Urbina, Roberto J.
dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorVega-Ochoa, Édgar A.
dc.contributor.authorLongoria-Gándara, Omar
dc.date.accessioned2022-03-14T22:54:47Z
dc.date.available2022-03-14T22:54:47Z
dc.date.issued2021-05
dc.descriptionThe continuously increasing bandwidth demand from new applications has led to the development of the new PCIe Gen6, reaching data rates of 64 GT/s and adopting PAM4 modulation scheme. While PAM4 solves the bandwidth constraint in high-speed interconnects, it brings new challenges for the physical channel analysis. Equalization (EQ) plays an important role even with PAM4 signaling. PCIe specification defines requirements to perform EQ at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients. Finding this subset of coefficients is timeconsuming,along with all the new challenges imposed by PAM4. In this paper, we propose an optimization approach for PCIe Gen6 link EQ. Our proposal is based on a suitable objective function formulated over the channel operating margin (COM), which is a new figure of merit (FOM) adopted by standards of communications for signaling speeds beyond 25 Gbps.es_MX
dc.description.sponsorshipITESO, A.C.es_MX
dc.identifier.citationR.J. Ruiz-Urbina, F.E. Rangel-Patiño, J.E. Rayas-Sánchez, E. A. Vega-Ochoa and O. Longoria-Gándara, “Transmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4,” in IEEE MTT-S Latin America Microwave Conf. (LAMC-2021), Cali, Colombia, May 2021, pp. 1-4. DOI: 10.1109/LAMC50424.2021.9601893es_MX
dc.identifier.isbn978-1-7281-9359-5
dc.identifier.urihttps://hdl.handle.net/11117/7862
dc.language.isoenges_MX
dc.publisherIEEEes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectChanneles_MX
dc.subjectCOMes_MX
dc.subjectCTLEes_MX
dc.subjectEqualization Mapses_MX
dc.subjectEye-diagrames_MX
dc.subjectFIRes_MX
dc.subjectISIes_MX
dc.subjectJitteres_MX
dc.subjectNRZes_MX
dc.subjectOptimizationes_MX
dc.subjectPAM4es_MX
dc.subjectPCIees_MX
dc.subjectPost-silicon Validationes_MX
dc.subjectReceiveres_MX
dc.subjectTransmitteres_MX
dc.titleTransmitter and receiver equalizers optimization for PCI Express Gen6.0 based on PAM4es_MX
dc.typeinfo:eu-repo/semantics/articlees_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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