Silicon Prototyping of Intel's Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits

Abstract

The purpose of this work is to document the most common problems encountered while implementing the layout of digital logic for Intel’s Horse Ridge II Cryo-CMOS SoC for Qubit control using Automatic Place and Route (APR) techniques and the solutions implemented for this design in the hope that it will serve as a guide to the novice SoC design engineer while implementing layout using APR tools and methodologies. The designs and techniques presented in this document are the result of the work experience acquired while working for Intel Labs’ Silicon Prototyping Team and represent the most notable problems found while implementing the Fully Integrated Cryo-CMOS SoC for state manipulation, readout, and high-speed gate pulsing of spin qubits Horse Ridge II), for which an IEEE publication is available from 2021 in the IEEE Journal of Solid-State Circuits. Although the IEEE paper describes the design implementation and the results from testing the fully integrated design, it does not describe the digital layout implementation or detail the challenges and solutions the team had to address to finalize the design. This document attempts to preserve the hard work of Intel’s silicon prototyping team in implementing the digital logic that interfaces with the analog portion of the design, as well as the full chip assembly flow for an Intel process. The problems and solutions documented here are presented in a way that will be helpful to novice SoC designers who encounter similar issues. Chapter 1 provides an overview of the project and details the implementation requirements we began with for the digital design. In Chapter 2, we cover the preparation of the collaterals required to implement the design, the full chip floor planning, partitioning, and partition implementation results, as well as the full chip assembly methodology. Chapter 3 details the methodology for timing, layout rules convergence, layout-versus-schematic (LVS) checks, and formal verification of the full chip against the final RTL model received from the RTL team.