Optimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulations

dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorPérez-Acosta, Luis N.
dc.contributor.authorMartínez-Guerrero, Esteban
dc.date.accessioned2013-05-21T17:03:04Z
dc.date.available2013-05-21T17:03:04Z
dc.date.issued2007-03
dc.descriptionWe propose in this work an optimization procedure for the design of a classical OTA-Miller CMOS integrated circuit. Our approach is based on a multi-objective minimax formulation to achieve the desired design specifications by numerical optimization. A brief description of the OTA-Miller is realized, showing its simulated responses at the starting point. The optimization procedure is described, including the definition of the error functions in terms of the design specifications, as well as the formulation of the corresponding minimax multi-objective function. Finally, the simulated optimized responses are reported. Our procedure is general enough to be applicable for the optimal design of other basic analog CMOS circuits, and it makes use of readily available software tools.es
dc.description.sponsorshipITESO, A.C.es
dc.description.sponsorshipConsejo Nacional de Ciencia y Tecnologíaes
dc.identifier.citationL. N. Pérez-Acosta, J. E. Rayas-Sánchez and E. Martínez-Guerrero, “Optimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulations,” in XIII International Workshop Iberchip (IWS 2007), Lima, Peru, Mar. 2007, pp. 387-390. (ISBN: 978-9972-242-09-0)es
dc.identifier.urihttp://hdl.handle.net/11117/591
dc.language.isoenges
dc.publisherXIII International Workshop Iberchipes
dc.relation.ispartofseriesInternational Workshop Iberchip;XIII
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectOTA-Miller CMOS Integrated Circuites
dc.subjectMinimax Multi-Objective Functiones
dc.titleOptimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulationses
dc.typeinfo:eu-repo/semantics/conferencePaperes
rei.peerreviewedYeses
rei.revisorXIII International Workshop Iberchip

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