Implementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology

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dc.contributor.advisorMartínez-Guerrero, Esteban
dc.contributor.authorMartínez-Flores, Iván
dc.date.accessioned2020-11-10T21:04:25Z
dc.date.available2020-11-10T21:04:25Z
dc.date.issued2020-08
dc.descriptionThis document presents the design of an arbiter circuit for a time-based SAR-ADC. The arbiter is a TSPC D flip flop. It was designed in TSMC 0.18 µm CMOS technology with 1.8 V supply voltage. It was tested at a clock frequency of 200 KHz, but it can operate even at 100 MHz. Simulation results using the typical process parameters shown a setup time of 5.02 ps and Hold time of 51.72 ps, the TSPC D flip flop power consumption is 62.61 µW@200 KHz, and the layout area is 368.284 µm2. The simulation is performed across all PVT corners that vary from a temperature of -40 °C up to 125 °C, with a supply voltage variation from 1.62 V up to 1.98 V and the TSPC D flip flop functionality is correct.es_MX
dc.description.sponsorshipITESO, A. C.es
dc.identifier.citationMartínez-Guerrero, E. (2020) Implementing a TSPC D Flip Flop as an Arbiter for a low power 10- bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.es_MX
dc.identifier.urihttps://hdl.handle.net/11117/6392
dc.language.isoenges_MX
dc.publisherITESOes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdfes_MX
dc.subjectTSPCes_MX
dc.subjectD FFes_MX
dc.subjectD Flip Flopes_MX
dc.titleImplementing a TSPC D Flip Flop as an Arbiter for a low power 10-bits 200kS/s ADC with Adaptive Conversion Cycle for High-Quality Audio Applications in 0.18um TSMC CMOS Technologyes_MX
dc.typeinfo:eu-repo/semantics/academicSpecializationes_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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