Test Module Design for ITESO TV1 SerDes
Cargando...
Archivos
Fecha
2015-12
Autores
Godínez-Maldonado, Ricardo
Título de la revista
ISSN de la revista
Título del volumen
Editor
ITESO
Resumen
Descripción
This document describes the work performed from January to November 2015 on the development of the Testing Module for the ITESO TV1 SerDes chip. The objective of this project is to design, test and manufacture a SerDes (Serializer/Deserializer) system for high speed communications on a 180 nm technology using the Cadence tools for integrated circuit design. The first section describes the background of the SerDes system; this section will explain the basic architecture of a SerDes Chip, its characteristics and applications. Next, an explanation of the technology available, some testing concepts and methodologies and the specifications for designing the chip are presented. Following this, a design proposal is presented by doing a summary of the requirements gathered for the implementation of this module and a description of its functionality. After that, a description on how the Testing Module design is implemented, this section shows the RTL design specifications and verification results. Lastly, the logic and physical synthesis of this module is explained, showing the results of the verification of this finalized RTL design.
Palabras clave
SerDes, Module Design
Citación
Godínez-Maldonado, R. (2015). Test Module Design for ITESO TV1 SerDes. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESO.