Accelerating Post-Silicon Debug: An Ensemble Machine Learning and Explainable AI Approach for Platform Boot Failures

dc.contributor.advisorGarcía-Espinosa, Eduardo
dc.contributor.authorMichel-Torres, David A.
dc.contributor.authorQuinones-Rivera, Jorge
dc.contributor.authorGarcía-Espinosa, Eduardo
dc.date.accessioned2026-02-04T19:56:30Z
dc.date.available2026-02-04T19:56:30Z
dc.date.issued2026-02
dc.description.abstractAs modern server platforms increase in complexity, debugging boot failures in FPGA-controlled power-up sequences becomes increasingly difficult, especially in post-silicon environments where reproducing issues is nontrivial and visibility is limited. This work introduces a machine learning-based framework for automatic classification of platform boot states by accessing Control and Status Register (CSR) data through the Board Management Controller (BMC) component. An ensemble model combining Neural Networks, Random Forest, Extreme Gradient Boosting (XGBoost), and a binary refinement classifier enables accurate differentiation across four platform boot conditions. The solution integrates Explainable Artificial Intelligence (XAI) techniques to highlight key signals that influence each decision, offering engineers insights for a faster triage. A Python-based inference script connects pre-silicon training and post-silicon deployment by mapping real-time hardware readings to the input format of the model. The experimental results demonstrate high accuracy, reduced boot state classification overlap, and effective generalization to previously unobserved datasets. This framework significantly improves the speed and clarity of post-silicon debug, reducing the dependency on traditional techniques.
dc.identifier.citationMichel-Torres, D. A. (2026). Accelerating Post-Silicon Debug: An Ensemble Machine Learning and Explainable AI Approach for Platform Boot Failures. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO.
dc.identifier.issn
dc.identifier.urihttps://hdl.handle.net/11117/12122
dc.language.isoeng
dc.publisherITESO
dc.relation.ispartofseries
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/deed.es
dc.subjectExplainable AI
dc.subjectHardware
dc.subjectAccuracy
dc.subjectTraining
dc.subjectServers
dc.subjectNeural Networks
dc.subjectPost-Silicon Validation
dc.subjectPower-Up Sequence
dc.subjectEnsemble Learning
dc.subjectMachine Learning
dc.subjectBoot State Classification
dc.subjectField Programmable Gate Arrays
dc.titleAccelerating Post-Silicon Debug: An Ensemble Machine Learning and Explainable AI Approach for Platform Boot Failures
dc.typeinfo:eu-repo/semantics/masterThesis
dc.type.versioninfo:eu-repo/semantics/publishedVersion

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