Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation

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dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorHakim, Nagib
dc.date.accessioned2019-08-30T19:01:23Z
dc.date.available2019-08-30T19:01:23Z
dc.date.issued2018-10
dc.descriptionAs microprocessor design scales to nanometric technology, traditional post-silicon validation techniques are inappropriate to get a full system functional coverage. Physical complexity and extreme technology process variations introduce design challenges to guarantee performance over process, voltage, and temperature conditions. In addition, there is an increasingly higher number of mixed-signal circuits within microprocessors. Many of them correspond to high-speed input/output (HSIO) links. Improvements in signaling methods, circuits, and process technology have allowed HSIO data rates to scale beyond 10 Gb/s, where undesired effects can create multiple signal integrity problems. With all of these elements, post-silicon validation of HSIO links is tough and time-consuming. One of the major challenges in electrical validation of HSIO links lies in the physical layer (PHY) tuning process, where equalization techniques are used to cancel these undesired effects. Typical current industrial practices for PHY tuning require massive lab measurements, since they are based on exhaustive enumeration methods. In this work, direct and surrogate-based optimization methods, including space mapping, are proposed based on suitable objective functions to efficiently tune the transmitter and receiver equalizers. The proposed methodologies are evaluated by lab measurements on realistic industrial post-silicon validation platforms, confirming dramatic speed up in PHY tuning and substantial performance improvement.es
dc.identifier.citationF. E. Rangel-Patiño, J. E. Rayas-Sánchez, and N. Hakim, “Transmitter and receiver equalizers optimization methodologies for high-speed links in industrial computer platforms post-silicon validation,” in Int. Test Conf. (ITC-2018), Phoenix, AZ, Oct. 2018, pp. 1-10. DOI: 10.1109/TEST.2018.8624794es
dc.identifier.issn1089-3539
dc.identifier.urihttp://hdl.handle.net/11117/6010
dc.language.isoenges
dc.publisherIEEEes
dc.relation.ispartofseriesInternational Test Conference (ITC-2018);
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectArtificial Neural Networks (ANN)es
dc.subjectChanneles
dc.subjectCrosstalkes
dc.subjectCTLEes
dc.subjectDoEes
dc.subjectEqualizationes
dc.subjectEthernetes
dc.subjectEye Diagrames
dc.subjectFIRes
dc.subjectHSIOes
dc.subjectISIes
dc.subjectJitteres
dc.subjectKriginges
dc.subjectMetamodelses
dc.subjectOptimizationes
dc.subjectPCIees
dc.subjectPost-silicon Validationes
dc.subjectReceiveres
dc.subjectSATAes
dc.subjectSFPes
dc.subjectSignal Integrityes
dc.subjectSpace Mappinges
dc.subjectSurrogateses
dc.subjectSystem Margininges
dc.subjectTransmitteres
dc.subjectTuninges
dc.subjectUSBes
dc.titleTransmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validationes
dc.typeinfo:eu-repo/semantics/articlees
rei.peerreviewedYeses

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