Analysis of the Implications of Stacked Devices in Nano-Scale Technologies for Analog Applications
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Fecha
2017-03
Autores
Lomelí-Illescas, Ismael
Solís-Bustos, Sergio A.
Rayas-Sánchez, José E.
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Editor
IEEE
Resumen
Descripción
In this work, a methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented. To evaluate the usage of stacked devices, the characteristic curves of transistors implemented with a different amount of transistors in stack are obtained and compared to those of a single device. The effects of using stacked devices are further studied with the implementation of a current mirror and the implementation of two different layout topologies, discussing their tradeoffs, advantages and drawbacks. Our methodology facilitates designers to develop a good understanding of the characteristics and limitations of a particular physical design before silicon is back for laboratory testing.
Palabras clave
Analog Layout, Channel Modulation, Interdigitated Layout, Leakage, Stacked Devices, Stack Effect
Citación
I. Lomelí-Illescas, S. A. Solís-Bustos, and J. E. Rayas-Sánchez, “Analysis of the implications of stacked devices in nano-scale technologies for analog applications,” in IEEE Latin American Test Symp. (LATS-2017), Bogota, Colombia, Mar. 2017, pp. 1-4. DOI: 10.1109/LATW.2017.7906750