Jitter Tolerance Acceleration Using the Golden Section Optimization Technique

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dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorBaca-Baylón, Ricardo
dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorDávalos-Santana, Miguel A.
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorRayas-Sánchez, José E.
dc.date.accessioned2019-08-30T19:11:32Z
dc.date.available2019-08-30T19:11:32Z
dc.date.issued2018-02
dc.descriptionPost-silicon validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of computer platforms under the current time-to-market (TTM) commitments. The goal of post-silicon validation for HSIO links is to confirm design robustness of both receiver (Rx) and transmitter (Tx) circuitry in a real application environment. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) through the link under worst stressing conditions. However, JTOL testing is very time-consuming when executing at specification BER, and the testing time is extremely increased when considering manufacturing process, voltage, and temperature (PVT) test coverage for a qualification decision. In order to speed up this process, we propose a new approach for JTOL testing based on the golden section algorithm. The proposed method takes advantage of the fast execution of the golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are seen. Our proposed methodology is validated by implementing it in a server HSIO link.es
dc.identifier.citationA. Viveros-Wacher, R. Baca-Baylón, F.E. Rangel-Patiño, M.A. Dávalos-Santana, E.A. Vega-Ochoa, and J.E. Rayas-Sánchez, “Jitter tolerance acceleration using the golden section optimization technique,” in IEEE Latin American Symp. Circuits and Systems Dig. (LASCAS 2018), Puerto Vallarta, Mexico, Feb. 2018, pp. 1-4. DOI: 10.1109/LASCAS.2018.8399908es
dc.identifier.issn2473-4667
dc.identifier.urihttp://hdl.handle.net/11117/6011
dc.language.isoenges
dc.publisherIEEEes
dc.relation.ispartofseriesIEEE Latin American Symposium Circuits and Systems (LASCAS 2018);
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectJitteres
dc.subjectJitter Tolerancees
dc.subjectHSIO Linkes
dc.subjectGolden Sectiones
dc.subjectBit Error Ratees
dc.subjectPost-silicon Validationes
dc.titleJitter Tolerance Acceleration Using the Golden Section Optimization Techniquees
dc.typeinfo:eu-repo/semantics/articlees
rei.peerreviewedYeses

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