DESI - Trabajos de fin de Maestría en Diseño Electrónico

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Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology
(ITESO, 2024-11) Jiménez-González, Mario A.; Martínez-Guerrero, Esteban; Aguilera-Galicia, Cuauhtémoc R.
This thesis presents a 12-bit ΣΔ ADC design on 45 nm CMOS technology for MEMS sensor applications. The design was performed using Virtuoso Cadence tools. The circuit is composed by a first-order ΣΔ Modulator, a CIC filter, and a Decimator. The first-order ΣΔ Modulator having an oversampling ratio K=128 is developed implementing the switched-capacitor technique. The first-order ΣΔ Modulator is composed by an integrator, a comparator, and a 1-bit DAC. Simulation results show how the Modulator changes the output transitions frequency depending on the input voltage value, being K=128 the best tradeoff between the number of modulations and circuit complexity. The physical design of this block is fully customized. For the digital filter and decimator blocks, a third-order Cascaded Integrator Comb (CIC) filter is developed as a Verilog macro model to test and measure the transient and spectral response of the ADC, as well as its main Figures of Merit.
Reporte de formación complementaria en área de concentración en diseño de sistemas digitales
(ITESO, 2018-09) Suárez-Lara, Roxana; Aguilera-Galicia, Cuauhtémoc R.; Fabila-García, Germán; Aguirre-Hernández, Mariano