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RISC-V Floating Point Unit
(ITESO, 2024-09) Alfaro-Gómez, Ricardo A.; Alvarado-Lagunes, Julián; Longoria-Gándara, Omar H.; Pizano-Escalante, José L.
This document explores the representation and processing of arithmetic data, with a focus on Floating Point (FP) operations for RISC-V architecture. It introduces the IEEE 754 standard for FP representation, detailing its evolution and significance in achieving portability and reliability in hardware units. Challenges associated with FP operations, such as high storage and execution costs, are addressed, necessitating dedicated Floating Point Units (FPUs) to optimize performance. The document proposes the implementation of an FPU for RISC-V architecture as a means to align with industry standards and contribute to scientific advancements. It discusses various number representations, the IEEE FP standard, and the role of FPUs within processor designs. Additionally, it outlines the problem statement, objectives, and expected impact of FPU implementation, providing insights into the division and square root algorithms used for FPU implementation. Overall, this document provides a comprehensive overview of FP operations, the IEEE 754 standard, FPU implementation challenges, and the significance of RISC-V architecture in contemporary computing.