Dynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical Applications
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This document presents the design of a Dynamic Comparator, a SR Latch and a Sample and Hold circuit for a 10 bits SAR ADC. Designs are performed using TSMC 0.18 um CMOS technology with 1.8 V supply voltage. The Dynamic comparator with Strong Arm topology is chosen to fulfill the requirements of SAR ADC. Its performance is tested at simulation level with a clock frequency of 10 KHz to 310 MHz, using typical parameter of process, nominal supply voltage and room temperature. Although, results are presented only at clock frequency of 100 KHz. This analysis showed that comparator has an input offset of 17.8 mV and power consumption of 36.27 nW. Power consumption is in the power budget of SAR ADC however, the input offset voltage has limited the resolution of SAR ADC. The SR latch is designed at transistor level using NAND gates. The circuit has additional digital logic and an external reset pin in order to avoid the prohibited condition. After implementing this modification, it shows a correct functionality at a clock frequency of 100 KHz. The sample and hold circuit is designed with a bootstrap switch for a load capacitance of 300 pF which is the total capacitance of the circuit when it is integrated to the SAR ADC.
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Castañeda-Villalpando, K. (2021). Dynamic Comparator, SR Latch and Bootstrap Switch for 10 Bits SAR ADC for Biomedical Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.