High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping

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dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorHakim, Nagib
dc.date.accessioned2019-08-29T20:32:09Z
dc.date.available2019-08-29T20:32:09Z
dc.date.issued2018-08
dc.descriptionOne of the major challenges in high-speed input/output (HSIO) links electrical validation is the physical layer (PHY) tuning process. Equalization techniques are employed to cancel any undesired effect. Typical industrial practices require massive lab measurements, making the equalization process very time consuming. In this paper, we exploit the Broyden-based input space mapping (SM) algorithm to efficiently optimize the PHY tuning receiver (Rx) equalizer settings for a SATA Gen 3 channel topology. We use a good-enough surrogate model as the coarse model, and an industrial post-silicon validation physical platform as the fine model. A map between the coarse and the fine model Rx equalizer settings is implicitly built, yielding an accelerated SM-based optimization of the PHY tuning process.es
dc.identifier.citationF. E. Rangel-Patiño, J. E. Rayas-Sánchez, A. Viveros-Wacher, E. A. Vega-Ochoa and N. Hakim, "High-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mapping," 2018 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO), Reykjavik, 2018, pp. 1-3. doi: 10.1109/NEMO.2018.8503099es
dc.identifier.isbn978-1-5386-5205-3
dc.identifier.urihttp://hdl.handle.net/11117/6000
dc.language.isoenges
dc.publisherIEEEes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes
dc.subjectAggressive Space Mappinges
dc.subjectBroydenes
dc.subjectDoEes
dc.subjectEye Diagrames
dc.subjectEqualizationes
dc.subjectHSIOes
dc.subjectMetamodelses
dc.subjectSATAes
dc.subjectSMes
dc.subjectSurrogate-based Optimizationes
dc.titleHigh-Speed Links Receiver Optimization in Post-Silicon Validation Exploiting Broyden-based Input Space Mappinges
dc.typeinfo:eu-repo/semantics/articlees
rei.peerreviewedYeses

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