Optimization of Decoupling Capacitors in Power Delivery Networks through Co-Simulation for Enhanced Signal and Power Integrity

Abstract

High-speed chiplet-based systems require simultaneous signal and power integrity considerations, as power-supply noise can significantly degrade communication performance. This paper presents a transient co-simulation methodology for the analysis and optimization of Universal Chiplet Interconnect Express (UCIe)-based interconnects that combines power delivery network modeling with high-speed channel simulation. The proposed framework optimizes bulk, cavity, and package-level decoupling capacitors using Nelder-Mead, Conjugate-Gradient, and Quasi-Newton algorithms, validated through voltage-stability and eye-diagram metrics. Among the three, the Quasi-Newton algorithm offers the best trade-off between convergence, efficiency, and capacitor count, confirming the methodology as a practical solution for power-delivery-network optimization in next-generation chiplet-based systems.