Test Modules Design for a SerDes Chip in 130 nm CMOS technology

Vista sencilla de ítem
dc.contributor.authorLimones-Mora, César F.
dc.contributor.directorGirón-Allende, Alexandro
dc.contributor.directorAvedaño-Fernández, Víctor
dc.date.accessioned2016-09-23T15:28:48Z
dc.date.available2016-09-23T15:28:48Z
dc.date.issued2016-07
dc.descriptionIn this thesis, a DFT architecture is proposed for testing a high-speed SerDes circuit. This architecture suggests the implementation of three testing modules: a comparator, a linear-feedback shift register (LFSR) and a signal driver. By embedding these test modules to the SerDes, the circuit will be able to perform eight different operating modes for testing in addition to the functional mode. With these operating modes, the functionality of all the modules individually and collectively can be tested by the use of multiplexers and BIST.es
dc.description.sponsorshipConsejo Nacional de Ciencia y Tecnologíaes
dc.identifier.citationLimones-Mora, C. F. (2016). Test Modules Design for a SerDes Chip in 130 nm CMOS technology. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas de Chip. Tlaquepaque, Jalisco: ITESOes
dc.identifier.urihttp://hdl.handle.net/11117/3892
dc.language.isoenges
dc.publisherITESOes
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-2.5-MX.pdfes
dc.subjectDFTes
dc.subjectSerializeres
dc.subjectDeserializeres
dc.subjectLFSRes
dc.subjectSerDeses
dc.subject130nmes
dc.subjectCMOSes
dc.subjectComparatores
dc.subjectRTLes
dc.subjectTest Moduleses
dc.titleTest Modules Design for a SerDes Chip in 130 nm CMOS technologyes
dc.typeinfo:eu-repo/semantics/academicSpecializationes
rei.peerreviewedYeses

Archivos

Bloque original
Mostrando 1 - 1 de 1
Miniatura
Nombre:
TOG Cesar Limones.pdf
Tamaño:
7.1 MB
Formato:
Adobe Portable Document Format
Descripción:
Descargar

Colecciones

DESI - Trabajos de fin de Especialidad en Diseño de Sistemas en Chip