Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology

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dc.contributor.advisorMartínez-Guerrero, Esteban
dc.contributor.advisorAguilera-Galicia, Cuauhtémoc R.
dc.contributor.authorJiménez-González, Mario A.
dc.date.accessioned2024-11-29T19:39:55Z
dc.date.available2024-11-29T19:39:55Z
dc.date.issued2024-11
dc.description.abstractThis thesis presents a 12-bit ΣΔ ADC design on 45 nm CMOS technology for MEMS sensor applications. The design was performed using Virtuoso Cadence tools. The circuit is composed by a first-order ΣΔ Modulator, a CIC filter, and a Decimator. The first-order ΣΔ Modulator having an oversampling ratio K=128 is developed implementing the switched-capacitor technique. The first-order ΣΔ Modulator is composed by an integrator, a comparator, and a 1-bit DAC. Simulation results show how the Modulator changes the output transitions frequency depending on the input voltage value, being K=128 the best tradeoff between the number of modulations and circuit complexity. The physical design of this block is fully customized. For the digital filter and decimator blocks, a third-order Cascaded Integrator Comb (CIC) filter is developed as a Verilog macro model to test and measure the transient and spectral response of the ADC, as well as its main Figures of Merit.
dc.identifier.citationJiménez-González, M. A. (2024). Design of a 12-bit Sigma Delta ADC in 45 nm CMOS technology. Trabajo de obtención de grado, Maestría en Diseño Electrónico. Tlaquepaque, Jalisco: ITESO.
dc.identifier.urihttps://hdl.handle.net/11117/11332
dc.language.isoeng
dc.publisherITESO
dc.rights.urihttps://creativecommons.org/licenses/by-nc/4.0/deed.es
dc.subjectADC
dc.subjectOTA
dc.subjectCMOS
dc.subjectIC Design
dc.subjectSigma-Delta
dc.subjectCIC Filter
dc.titleDesign of a 12-bit Sigma Delta ADC in 45 nm CMOS technology
dc.typeinfo:eu-repo/semantics/masterThesis
dc.type.versioninfo:eu-repo/semantics/acceptedVersion

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