A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization





López-Araiza, Karla G.
Rangel-Patiño, Francisco E.
Ascencio-Blancarte, Jorge E.
Vega-Ochoa, Edgar A.
Rayas-Sánchez, José E.
Longoria-Gandara, Omar

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The continuously increasing bandwidth demand from new applications has led to the development of the new peripheral component interconnect express (PCIe) Gen6, reaching data rates of 64 giga-transfers per second (GT/s) and adopting the pulse amplitude modulation 4-level (PAM4) signaling scheme. While PAM4 solves the bandwidth requirements, it brings new challenges for the physical channel design. PAM4 is more susceptible to errors due to various noise sources caused by reduced voltage (and timing) ranges, yielding a higher bit error rate (BER). It also introduces new challenges in slicers, transition jitter, and equalizers, making of equalization (EQ) a critical process for PAM4 signaling. In this paper, we propose a multi-stage continuous-time linear equalizer (CTLE) with high-band, mid-band, and low-band frequency boost stages to deal with highly lossy channels. Given the complexity of EQ of multi-level signals, optimization techniques are used, including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning.

Palabras clave

Channel, CTLE, Equalization, Eye-diagram, FIR, ISI, Jitter, Optimization, PAM4, PCIe, Receiver, Transmitter


K. G. López-Araiza, F. E. Rangel-Patiño, J. E. Ascencio-Blancarte E. A. Vega-Ochoa, J. E. Rayas-Sánchez, and O. Longoria-Gándara, “A multi-stage CTLE design and optimization for PCI Express Gen6.0 link equalization,” in IEEE Latin American Electron Devices Conf. (LAEDC), Puebla, Mexico, Jul. 2023, pp. 1-4.