A Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalization

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dc.contributor.authorLópez-Araiza, Karla G.
dc.contributor.authorRangel-Patiño, Francisco E.
dc.contributor.authorAscencio-Blancarte, Jorge E.
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorLongoria-Gandara, Omar
dc.date.accessioned2023-08-14T22:46:49Z
dc.date.available2023-08-14T22:46:49Z
dc.date.issued2023-07
dc.descriptionThe continuously increasing bandwidth demand from new applications has led to the development of the new peripheral component interconnect express (PCIe) Gen6, reaching data rates of 64 giga-transfers per second (GT/s) and adopting the pulse amplitude modulation 4-level (PAM4) signaling scheme. While PAM4 solves the bandwidth requirements, it brings new challenges for the physical channel design. PAM4 is more susceptible to errors due to various noise sources caused by reduced voltage (and timing) ranges, yielding a higher bit error rate (BER). It also introduces new challenges in slicers, transition jitter, and equalizers, making of equalization (EQ) a critical process for PAM4 signaling. In this paper, we propose a multi-stage continuous-time linear equalizer (CTLE) with high-band, mid-band, and low-band frequency boost stages to deal with highly lossy channels. Given the complexity of EQ of multi-level signals, optimization techniques are used, including an efficient optimization of the transmitter finite impulse response (FIR) filter and the receiver CTLE tuning.es_MX
dc.description.sponsorshipITESO, A.C.es_MX
dc.identifier.citationK. G. López-Araiza, F. E. Rangel-Patiño, J. E. Ascencio-Blancarte E. A. Vega-Ochoa, J. E. Rayas-Sánchez, and O. Longoria-Gándara, “A multi-stage CTLE design and optimization for PCI Express Gen6.0 link equalization,” in IEEE Latin American Electron Devices Conf. (LAEDC), Puebla, Mexico, Jul. 2023, pp. 1-4.es_MX
dc.identifier.isbn979-8-3503-1191-4
dc.identifier.issn2835-3463
dc.identifier.urihttps://hdl.handle.net/11117/9646
dc.language.isoenges_MX
dc.publisherIEEEes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectChanneles_MX
dc.subjectCTLEes_MX
dc.subjectEqualizationes_MX
dc.subjectEye-diagrames_MX
dc.subjectFIRes_MX
dc.subjectISIes_MX
dc.subjectJitteres_MX
dc.subjectOptimizationes_MX
dc.subjectPAM4es_MX
dc.subjectPCIees_MX
dc.subjectReceiveres_MX
dc.subjectTransmitteres_MX
dc.titleA Multi-Stage CTLE Design and Optimization for PCI Express Gen6.0 Link Equalizationes_MX
dc.typeinfo:eu-repo/semantics/articlees_MX
dc.type.versioninfo:eu-repo/semantics/publishedVersiones_MX

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