Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas
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Fecha
2021-07
Autores
Garza-Pérez, Raymundo
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ITESO
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This document presents the design of a successive approximation register (SAR) and a digital to analog converter (DAC). The two circuits are designed, synthesized, and implemented in layout using TSMC 180nm technology. The DAC has a Charge-Scaling Capacitors architecture and uses a switching scheme different to the conventional one, which improves the power consumption of the circuit. These modules are used in a low power 10-bit ADC and are designed for Biomedical applications. The SAR design is synthesized using a clock with a frequency of 250 MHz, the total power consumption of the SAR is 22045.030 uW. A testbench is designed to verify the functionality of the SAR by testing several cases of interest. The base capacitance of the DAC is 1 pF. The functionality of the DAC is tested using a mixed signal simulator and a testbench with the required circuit. This also includes the Verilog model of the SAR block. The testbench is able to apply single conversions test case and a ramp-test case, in which all the possible inputs to the DAC are tested sequentially.
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Garza-Pérez, R. (2021). Registro de aproximaciones sucesivas y convertidor digital a analógico para SAR ADC de 10 bits de baja potencia para aplicaciones biomédicas. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.