Fast jitter tolerance testing for high-speed serial links in post-silicon validation

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dc.contributor.authorViveros-Wacher, Andrés
dc.contributor.authorBaca-Baylón, Ricardo
dc.contributor.authorSilva-Cortés, Johana L.
dc.contributor.authorVega-Ochoa, Edgar A.
dc.contributor.authorRayas-Sánchez, José E.
dc.contributor.authorRangel-Patiño, Francisco E.
dc.date.accessioned2022-04-29T21:36:59Z
dc.date.available2022-04-29T21:36:59Z
dc.date.issued2021-11
dc.descriptionPost-silicon electrical validation of high-speed input/output (HSIO) links is a critical process for product qualification schedules of high-performance computer platforms under current aggressive time-to-market (TTM) commitments. Improvements in signaling methods, circuits, and process technologies have allowed HSIO data rates to scale well beyond 10 Gb/s. Noise and EM effects can create multiple signal integrity problems, which are aggravated by continuously faster bus technologies. The goal of post-silicon validation for HSIO links is to ensure design robustness of both receiver (Rx) and transmitter (Tx) circuitry in real system environments. One of the most common ways to evaluate the performance of a HSIO link is to characterize the Rx jitter tolerance (JTOL) performance by measuring the bit error rate (BER) of the link under worst stressing conditions. However, JTOL testing is extremely time-consuming when executed at specification BER considering manufacturing process, voltage, and temperature (PVT) test coverage. In order to significantly accelerate this process, we propose a novel approach for JTOL testing based on an efficient direct search optimization methodology. Our approach exploits the fast execution of a modified golden section search with a high BER, while overcoming the lack of correlation between different BERs by performing a downward linear search at the actual target BER until no errors are found. Our proposed methodology is validated in a realistic industrial server post-silicon validation platform for three different computer HSIO links: SATA, USB3, and PCIe3.es_MX
dc.description.sponsorshipITESO, A.C.es_MX
dc.identifier.citationA. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, J. L. Silva-Cortés, E. A. Vega-Ochoa, and J. E. Rayas-Sánchez, “Fast jitter tolerance testing for high-speed serial links in post-silicon validation,” IEEE Trans. Electromagnetic Compatibility., early access version, 2022.es_MX
dc.identifier.issn0018-9375
dc.identifier.urihttps://hdl.handle.net/11117/7959
dc.language.isoenges_MX
dc.publisherIEEEes_MX
dc.rights.urihttp://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdfes_MX
dc.subjectbit error ratees_MX
dc.subjectgolden sectiones_MX
dc.subjectHSIO linkes_MX
dc.subjectISIes_MX
dc.subjectJitteres_MX
dc.subjectjitter tolerancees_MX
dc.subjectPCIees_MX
dc.subjectpost-silicon validationes_MX
dc.subjectSATAes_MX
dc.subjectUSBes_MX
dc.titleFast jitter tolerance testing for high-speed serial links in post-silicon validationes_MX
dc.typeinfo:eu-repo/semantics/articlees_MX
dc.type.versioninfo:eu-repo/semantics/acceptedVersiones_MX

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