Diseño del path de alta frecuencia del receptor analógico del SerDes ITESOTV1
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Fecha
2015-12
Autores
Gallardo-García, Omar
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Editor
ITESO
Resumen
Descripción
This report presents the design of the high frequency path from the Analog receptor of the first test vehicle of the SerDes ITESOTV1. The high frequency path is conformed for the high frequency amplifier core, this core is composed of two operational transconductance amplifiers connected in cascade mode and a fully differential ton single ended signal converter. The report starts with an introduction of the scope of the SerDes ITESOTV1 project where the characteristics, requirements, limitations and the considerations of the resources for the development of the project are defined. The methodology for the design of the high frequency path is described step by step with detail so the work can be replicated for any person interested in it. The methodology describes the equations and the calculus realized for the stage of the amplification design, and also with the approach of the challenges encountered through the design and justification of the chosen decisions.
Besides the design for this SerDes module, all the tests developed in each of the stages of the design are described showing schematics test benches and plots of the results obtained from the simulations in the frequency and time domain. Finally, the approach of the considerations taken to achieve a correct layout in each of the parts that built the core receptor of the SerDes and displays the images of the physical design realized.
Palabras clave
SerDes, Core, Receptor Analógico
Citación
Gallardo-García, O. (2015). Diseño del path de alta frecuencia del receptor analógico del SerDes ITESOTV1. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO.